METHOD AND SYSTEM FOR QUEUING TRANSFERS OF MULTIPLE NON-CONTIGUOUS ADDRESS RANGES WITH A SINGLE COMMAND

• US 20100161936A1
• Filed: 12/22/2008
• Published: 06/24/2010
• Est. Priority Date: 12/22/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: HUFFMAN, AMBER, ROYER, ROBERT
• Granted Patent: US 9,128,699 B2
• Time in Patent Office: Days
• US Class Current: 711/209
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0671 In-line storage system
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction

Abstract

Methods and systems for queuing transfers of multiple non-contiguous address ranges within a single command are disclosed. Embodiments of systems include system processors, memory to store data and executable software, and storage devices to receive transfer commands stored in system memory. A host controller interface driver is executed by one or more system processors and collects multiple non-continuous address ranges from storage-device transfer requests and records starting addresses and quantities of data to transfer for each non-continuous range in a tagged command list. It records the number of address ranges in the tagged command list, and a tagged-transfer opcode in a command, and stores the command and the tagged command list in a command table for the storage device. It records a base address for the command table in memory and an offset for the tagged command list into a command header, which is stored in a command queue.

Claims

1. A method for queuing a plurality of transfers associated with a single command, the method comprising:

sending a single command over an interface to request a storage device to transfer of a plurality of non-continuous address ranges; and

receiving a single interrupt upon completion of the transfer of the plurality of non-continuous address ranges.

2. The method of claim 1 wherein said interface is a Serial ATA (Advanced Technology Attachment) bus interface.

3. The method of claim 1 wherein said interface is a SCSI (Small Computer System Interface).

4. The method of claim 1 wherein said interface is a SAS (Serial Attached SCSI) interface.

5. The method of claim 1 wherein said interface is an Advanced Host Controller Interface (AHCI).

6. The method of claim 5 wherein said interface is for a Serial ATA (Advanced Technology Attachment) storage device.

7. The method of claim 1 wherein said interface is a Non-Volatile Memory Host Controller Interface (NVMHCI).

8. The method of claim 6 wherein said interface is for a NAND flash memory storage device.

9. The method of claim 6 wherein said interface is for a phase-change memory storage device.

10. A method for requesting transfer of a plurality of non-contiguous address ranges in a storage device, the method comprising:

recording for each of the plurality of non-continuous address ranges, a starting address and quantity of data to transfer, in a tagged command list;

recording a count of the number of non-contiguous address ranges, recorded in the tagged command list, and a tagged-transfer opcode in a command, said command and said tagged command list being stored in a command table in a memory; and

recording a base address for the command table in memory and an offset for the tagged command list in a command header, said command header being one of a plurality of command headers stored in a command queue.

11. The method of claim 10 comprising:

producing a command packet for a Serial ATA bus interface at least from the recorded base address for the command table in memory and the offset for the tagged command list in said command header and from the recorded count of the number of non-contiguous address ranges in said command.

12. The method of claim 10 wherein said command queue is for an Advanced Host Controller Interface (AHCI).

13. The method of claim 10 wherein said command queue is for a Non-Volatile Memory Host Controller Interface (NVMHCI).

14. The method of claim 10 wherein said command queue is for a SAS (Serial Attached SCSI) interface.

15. An article of manufacture including a machine readable medium, said machine readable medium storing state and/or executable data, which when accessed by one or more machines causes said one or more machines to:

collect a plurality of non-continuous address ranges from a corresponding plurality of transfer requests;

record for each of the plurality of non-continuous address ranges, a starting address and quantity of data to transfer, in a tagged command list;

record a count of the number of non-contiguous address ranges, recorded in the tagged command list, and a tagged-transfer opcode in a command, said command and said tagged command list being stored in a command table in a memory; and

record a base address for the command table in memory and an offset for the tagged command list in a command header, said command header being one of a plurality of command headers stored in a command queue.

16. The article of manufacture of claim 15, said machine readable medium storing state and/or executable data, which when accessed by one or more machines causes said one or more machines to:

produce a command packet for a Serial ATA bus interface at least from the recorded base address for the command table in memory and the offset for the tagged command list in said command header and from the recorded count of the number of non-contiguous address ranges in said command.

17. The article of manufacture of claim 15 wherein said command queue is for an Advanced Host Controller Interface (AHCI).

18. The article of manufacture of claim 15 wherein said command queue is for a Non-Volatile Memory Host Controller Interface (NVMHCI).

19. The article of manufacture of claim 15 wherein said command queue is for a SAS (Serial Attached SCSI) interface.

20. A system for requesting transfer of a plurality of non-contiguous address ranges with a single command, the system comprising:

a one or more system processors;

a system memory to store data and executable software;

a storage device coupled with the system memory to receive transfer commands stored in the system memory; and

an processor executable host controller interface driver stored in the system memory that when executed by the one or more system processors causes said to one or more system processors to;

collect a plurality of non-continuous address ranges from a corresponding plurality of storage-device transfer requests;

record for each of the plurality of non-continuous address ranges, a starting address and quantity of data to transfer, in a tagged command list;

record a count of the number of non-contiguous address ranges, recorded in the tagged command list, and a tagged-transfer opcode in a command, said command and said tagged command list being stored in a command table in the system memory for said storage device; and

record a base address for the command table in memory and an offset for the tagged command list in a command header, said command header being one of a plurality of command headers stored in a command queue.

21. The system of claim 20 wherein said host controller interface is an Advanced Host Controller Interface (AHCI) for a Serial ATA (Advanced Technology Attachment).

22. The system of claim 20, wherein said processor executable host controller interface driver, when executed by the one or more system processors further causes said to one or more system processors to:

produce a command packet for a Serial ATA bus interface at least from the recorded base address for the command table in memory and the offset for the tagged command list in said command header and from the recorded count of the number of non-contiguous address ranges in said command.

23. The system of claim 20 wherein said host controller interface is a Non-Volatile Memory Host Controller Interface (NVMHCI).

24. The system of claim 23 wherein said host controller interface is for a NAND flash memory storage device.

25. The system of claim 23 wherein said host controller interface is for a phase-change memory storage device.