PROCESSOR AND METHOD FOR RECOVERING GLOBAL HISTORY SHIFT REGISTER AND RETURN ADDRESS STACK THEREOF
First Claim
1. A method for recovering a global history shift register (GHSR) of an instruction pipeline of a processor, the method comprising:
- providing a branch recovery table (BRT);
adding a record to the BRT according to each of a plurality of branch instructions when said branch instruction enters a predetermined stage of the instruction pipeline;
determining a removal range of the BRT according to a condition which triggers a pipeline flush of the instruction pipeline;
removing all records in the removal range; and
recovering the GHSR of the instruction pipeline according to the removed records.
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Accused Products
Abstract
A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records.
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Citations
24 Claims
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1. A method for recovering a global history shift register (GHSR) of an instruction pipeline of a processor, the method comprising:
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providing a branch recovery table (BRT); adding a record to the BRT according to each of a plurality of branch instructions when said branch instruction enters a predetermined stage of the instruction pipeline; determining a removal range of the BRT according to a condition which triggers a pipeline flush of the instruction pipeline; removing all records in the removal range; and recovering the GHSR of the instruction pipeline according to the removed records. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for recovering a return address stack (RAS) of an instruction pipeline of a processor, the method comprising:
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providing a branch recovery table (BRT); adding a record to the BRT according to one of a plurality of branch instructions, when said branch instruction enters a predetermined stage of the instruction pipeline; providing a backup stack; pushing a first return address into the backup stack whenever the first return address is popped out from the RAS of the instruction pipeline; determining a removal range of the BRT according to a condition which triggers a pipeline flush of the instruction pipeline; recovering the RAS according to the records in the removal range and the backup stack; and removing all records in the removal range. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A processor comprising an instruction pipeline, the instruction pipeline comprising:
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a global history shift register (GHSR); and a storage apparatus, coupled to the GHSR through the instruction pipeline and storing a branch recovery table (BRT), wherein when each of a plurality of branch instructions enters a predetermined stage of the instruction pipeline, the processor adds a record in the BRT according to said branch instruction; and when flushing the instruction pipeline, the processor determines a removal range of the BRT according to a condition which triggers the pipeline flush, removes all records in the removal range, and recovers the GHSR according to the removed records. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A processor, comprising an instruction pipeline, the instruction pipeline comprising:
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a return address stack (RAS), a backup stack, and a storage apparatus, storing a branch recovery table (BRT);
whereinthe RAS, the backup stack, and the storage apparatus are coupled to each other through the instruction pipeline; when each of a plurality of branch instructions enters a predetermined stage of the instruction pipeline, the processor adds a record in the BRT according to said branch instruction; whenever the processor pops out a first return address from the RAS, the processor pushes the first return address into the backup stack; and when flushing the instruction pipeline, the processor determines a removal range of the BRT according to a condition which triggers the pipeline flush, recovers the RAS according to the records in the removal range and the backup stack, and removes all records in the removal range. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification