Memory System having Spare Memory Devices Attached to a Local Interface Bus

• US 20100162037A1
• Filed: 12/22/2008
• Published: 06/24/2010
• Est. Priority Date: 12/22/2008
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wright, Kenneth Lee, Gower, Kevin C., Maule, Warren Edward
• Application Number:
  US12/341,472
• Publication Number:
  US 20100162037A1
• Time in Patent Office: Days
• US Class Current: 714/5
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 29/83 with reduced power consumption
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system includes a memory controller, one or more memory channel(s), and a memory subsystem having a memory interface device (e.g. a hub or buffer device) located on a memory subsystem (e.g. a DIMM) coupled to the memory channel to communicate with the memory device(s) array. This buffered DIMM is provided with one or more spare chips on the DIMM, wherein the data bits sourced from the spare chips are connected to the memory hub device and the bus to the DIMM includes only those data bits used for normal operation. The buffered DIMM with one or more spare chips on the DIMM has the spare memory shared among all the ranks, and the memory hub device includes separate control bus(es) for the spare memory device to allow the spare memory device(s) to be utilized to replace one or more failing bits and/or devices within any rank of memory in the memory subsystem.

Claims

1. A computer memory system, comprising a memory controller, one or more memory bus channel(s), a local memory interface device for a memory subsystem which is coupled to one of said memory bus channels to communicate with devices of a memory array over said memory bus channel for normal memory operations.

2. The computer memory system according to claim 1 wherein said local interface device is a buffered hub located on a memory module.

3. The computer memory system according to claim 1 wherein said memory subsystem is a DIMM provided with one or more spare memory devices on the DIMM, and data bits sourced from the spare memory devices are connection to a buffered hub and the memory bus channel.

4. The computer memory system according to claim 1 wherein said memory subsystem has said local memory interface located on a memory module subsystem, and the memory module subsystem is provided with one or more spare devices, and data bits sourced from said spare devices are connected to said local memory interface and a memory bus channel to said memory module from said memory controller includes only those data bits used for normal operation.

5. The computer memory system according to claim 3 where one or more spare memory devices are located on said DIMM and shared among all ranks on the DIMM.

6. The computer memory system according to claim 3 where said local memory interface has one or more separate control buses for said spare device and said spare memory is coupled to replace one or more failing bits and/or memory devices within any rank of memory in the memory subsystem.

7. The computer memory system according to claim 6 wherein said separate control busses utilize separate and programmable CS (chip select) and CKE (clock enable signals for unique selection and power management of spare devices.

8. The computer system according to claim 1 wherein said local memory interface and said memory controller are coupled to enable transparent monitoring of the state of a spare device to verify that it is functioning properly after it is employed as a spare.

9. The computer system according to claim 1 wherein there are provided x memory devices which may be accessed in parallel including those which are normally accessed and those provided for spare memory, wherein for the x memory devices there are y data bits which may be accessed, and wherein those for normally accessed memory have a data width of z and the number of y data bits is greater than the data width of z, said subsystem local memory interface having a circuit to enable the local memory interface to redirect one or more bits from the normally accessed memory devices to one or more bits of a spare memory device while maintaining the original interface data width of z.

10. The computer system according to claim 1 wherein one or more spare chips are placed in a reset state for low power until invoked, thereby reducing overall memory subsystem power.

11. The computer system according to claim 1 wherein spare chips are placed in a self refresh or another low power state until required to be invoked to reduce power.

12. The computer system according to claim 1 wherein power to the memory subsystem is the same before and after spare devices are invoked for utilization to replace a failing memory and wherein even with the use of spare memory devices the memory utilizes only power levels of the memory subsystem used before any spare memory devices are invoked.

13. The computer system according to claim 1 wherein said memory devices are employed for the storing and retrieval of data and ECC information.

14. The computer system according to claim 1 wherein the local memory interface provides circuits to change the operating state, utilization of power and wherein the width of the memory controller interface is not increased to accommodate any spare memory devices, whether or not the memory controller interface is buffered or unbuffered by said local memory interface.

15. A memory system comprising a memory controller and memory module(s) including at least one local communication interface hub device(s), a rank of memory device(s) and spare memory device(s) which communicate by way of said hub device(s) which are cascade-interconnected.

16. A memory of operation of plurality of memory modules each having a rank of memory devices and a memory controller, comprising the steps of processing storage and retrieval requests for data and EDC check bits for addresses of memory devices, said rank including one or more additional memory devices which have the same data width and addressing as the memory devices, and using said additional memory devices as a spare memory device by a local memory interface to replace a failing memory device, wherein the memory interface between the modules and memory controller transfers read and write data in groups of bits, over one or more transfers, to selected memory devices, and using said a spare memory device as replace a replacement for a failing memory device, the data is written to both the original and failing memory device as well as to its spare device which has been activated by said local memory interface to replace the failing memory device, and during read operations, the exemplary memory interface device reads data from memory devices in addition to the spare memory device and replaces the data from failing memory device, with the data from the spare memory device which has been activated by the memory interface device to provide the data originally intended to be read from failing memory device.

17. A memory system comprising a memory controller and memory module(s) including at least one local communication interface hub device(s), a rank of memory device(s) and spare memory device(s) which communicate by way of said hub device(s) which are connected to each other and the memory controller using multi-drop bus(es).

18. A memory of operation of plurality of memory modules each having a rank of memory devices and a memory controller, comprising the steps of processing storage and retrieval requests for data and EDC check bits for addresses of memory devices, said rank including one or more additional memory devices which have the same data width and addressing as the memory devices, and using said additional memory devices as a spare memory device by a local memory interface to replace a failing memory device, wherein the memory interface between the modules and memory controller transfers read and write data in groups of bits, over one or more transfers, to selected memory devices, and using said a spare memory device as replace a replacement for a failing memory device, the data is written to both the original and failing memory device as well as to its spare device which has been activated by said local memory interface to replace the failing memory device, said memory module being coupled to a multi-drop bus memory system that includes a memory bus which includes a bi-directional data bus and a bus used to transfer address, command and control information from memory controller to one or more memory modules wherein data and address buses respectively connect said memory controller to one or more memory modules in a multi-drop nature without re-driving signals from one memory modules to another memory module or to said memory controller, said local memory device including a buffer device which re-drives data, address, command and control information associated with accesses to memory and said memory modules include trace lengths to the buffer of said memory interface device, such that a short stub length exists at each memory module position.

19. A memory of operation of plurality of memory modules of a memory subsystem having a rank of memory devices and a memory controller, comprising the steps of passing read and write information over a memory interface device located on a memory subsystem to communicate with the memory device(s) of the memory module, and sourcing and storing data bits of a spare memory device coupled to said memory interface device and to a memory channel connected to the memory module over which data bits used for normal operations pass, said spare memory device sharing all of the ranks on the memory module and utilized to replace one or more failing bits and/or devices within any rank of memory in the memory subsystem, said channel to the memory module passing control command signals over said memory interface device to said memory devices and the spare memory for power management of the spare memory.

20. The method according to claim 19 wherein said memory module is monitored to detect failing bits and/or devices and upon detection of a failure the spare memory is invoked and activated from a reset state of power to a normal powered on state for a memory device and one or more bits from the normally accessed memory devices are redirected to one or more bits of a spare memory device while maintaining the original interface data width with the power of the memory subsystem being the same before and after the spare devices are utilized to replace a failing memory device.