Protecting integrity of data in multi-layered memory with data redundancy

• US 20100162065A1
• Filed: 09/21/2009
• Published: 06/24/2010
• Est. Priority Date: 12/19/2008
• Status: Abandoned Application

• Current Assignee: III Holdings 1, LLC
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Norman, Robert
• Application Number:
  US12/586,416
• Publication Number:
  US 20100162065A1
• Time in Patent Office: Days
• US Class Current: 714/746
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H03M 7/30 Compression speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

Abstract

Systems, integrated circuits, and methods for protecting data stored in third dimensional vertically stacked memory technology are disclosed. An integrated circuit is configured to perform duplication of data disposed in multi-layered memory that can comprise two-terminal cross-point memory arrays fabricated BEOL on top of a FEOL logic layer that includes active circuitry for performing data operations (e.g., read, write, program, and erase) on the multi-layered memory. For example, the integrated circuit can include a first subset of BEOL memory layers configured to store data, a second subset of the BEOL memory layers configured to store a copy of the data from the first subset of memory layers, a FEOL redundancy circuit coupled to the first subset of the memory layers and the second subset of the memory layers, the redundancy circuit being configured to provide both a portion of the data and a copy of the portion of the data.

Claims

1. An apparatus, comprising:

a substrate;

a first subset of memory cells in multiple memory layers configured to store data;

a second subset of memory cells in the multiple memory layers configured to store a copy of the data, the first and second subsets of the multiple memory layers are in contact with the substrate and are fabricated directly above the substrate; and

active circuitry fabricated on the substrate and positioned below the multiple memory layers, the active circuitry including a redundancy circuit electrically coupled with the first subset of memory cells and the second subset of memory cells, the redundancy circuit configured to access the first subset of memory cells to store the data and to access the second subset of memory cells to store the copy of the data,

wherein any of the multiple memory layers is configured to include the first subset of memory cells and the second subset of memory cells.

2. The apparatus of claim 1, wherein the active circuitry includes a control module configured to write the data to the first subset of memory cells, and to write the copy of the data to the second subset of memory cell, wherein the copy of the data is written substantially simultaneously to the multiple memory layers.

3. The apparatus of claim 1, wherein the active circuitry includes a control module configured to write the data to the first subset of memory cells and to write the copy of the data to the second subset of memory cell without an erase operation that precedes the writing of the data or the writing of the copy of the data.

4. The apparatus of claim 1, wherein the first subset of memory cells and the second subset of memory cells further comprises memory cells configured to store data as a plurality of conductivity profiles that are retained in the absence of power.

5. The apparatus of claim 1 and further comprising:

interleaved layers of memory in the multiple memory layers, wherein layers of memory to store the copy of the data are interleaved with layers of memory to store the data.

6. The apparatus of claim 1 and further comprising:

at least two layers including the first subset of memory cells to store the data; and

at least one layer including the second subset of memory cells to store the copy of the data, wherein the at least one layer including the second subset of memory cells is between the at least two layers including the first subset of memory cells.

7. The apparatus of claim 1, wherein the active circuitry includes

a first subset of drivers configured to access the first subset of memory cells in a first subset of the multiple memory layers, and

a second subset of drivers configured to access the second subset of memory cells in a second subset of the multiple memory layers.

8. The apparatus of claim 7, wherein the active circuitry includes

a first decoder coupled electrically coupled with the first subset of drivers and with the second subset of drivers, wherein the first decoder is configured to provide data to the first subset of drivers and the second subset of drivers.

9. The apparatus of claim 7, wherein the active circuitry includes

first decoder electrically coupled with the first subset of drivers, and

a second decoder electrically coupled with the second subset of drivers, wherein the first decoder and the second decoder are configured to provide data to the first subset of drivers and the second subset of drivers, respectively.

10. The apparatus of claim 1, wherein the active circuitry includes

an access selector configured to detect a write operation in association with a portion of the multiple memory layers, and to select whether to suppress generation of the copy of the data.

11. The apparatus of claim 1, wherein the active circuitry includes

an access selector configured to select two layers of the multiple memory layers to respectively access the first subset of memory cells and the second subset of memory cells during a read operation.

12. The apparatus of claim 1 and wherein the redundancy circuit further comprises an error detection module configured to detect a mismatch between the data in the first subset of memory cells and the copy of the data in the second subset of memory cells.

13. The apparatus of claim 12, wherein the error detection module is further configured to generate an error flag signal indicating the mismatch.

14. The apparatus of claim 12, wherein the error detection module is further configured upon detection of the mismatch, to select the copy of the data and to provide the copy of the data as read data.

15. The apparatus of claim 1, wherein the first subset of memory cells and the second subset of memory cells are configured to be read substantially in parallel to compare the data and the copy of the data, respectively.

16. An integrated circuit, comprising:

a substrate including active circuitry fabricated on the substrate;

a first memory block fabricated directly above the substrate and configured to store a datum, the first memory block including a memory cell configured to store the datum based on a conductivity profile of the memory cell;

a second memory block fabricated directly above the substrate and configured to store a duplicate of the datum, the second memory block including another memory cell configured to store the datum based on a conductivity profile of the another memory cell; and

a redundancy circuit included in the active circuitry and positioned below the first and second memory blocks, the redundancy circuit electrically coupled with the first and the second memory blocks, the redundancy circuit configured to duplicate the datum and to write the datum to both the first memory block and the second memory block.

17. The integrated circuit of claim 16, wherein the redundancy circuit further comprises a controller configured to detect a mismatch between the datum and the duplicate of the datum, and to recover the datum.

18. The integrated circuit of claim 16, wherein the redundancy circuit is configured to duplicate the datum by generating one or more copies of the datum and to store the one or more copies of the datum within the second memory block.

19. The integrated circuit of claim 16, wherein the memory cell and the another memory cell comprise third dimension memory cells.

20. The integrated circuit of claim 16 and further comprising:

a single layer of memory wherein the first memory block and the second memory block reside in the single layer or memory.

21. The integrated circuit of claim 16 and further comprising:

two or more layers of memory, wherein the first memory block and the second memory block reside in separate layers of the two or more layers of memory.

22. The integrated circuit of claim 16, wherein the redundancy circuit includes a portion of a memory layer being configured to store wait-state data associated with a recovery operation.

23. The integrated circuit of claim 16, wherein the active circuitry further includes an access selector configured to detect a write operation in association with a portion of the first memory block and operative to select whether to suppress duplication of the datum in the second memory block.

24. A method for non-volatile data redundancy, comprising:

writing data substantially simultaneously to at least two blocks of non-volatile memory in an array of resistance-based memory cells that are fabricated directly above a substrate including active circuitry fabricated on the substrate and configured to perform data operations on the array;

storing the data in the at least two blocks of non-volatile memory; and

comparing the data stored in the at least two blocks of non-volatile memory to detect a mismatch by reading the data from the at least two blocks of non-volatile memory substantially simultaneously.

25. The method of claim 24 and further comprising initiating a recovery operation to reduplicate the data in at least one of the two blocks of non-volatile memory.