FLASH MEMORY CONTROLLER, ERROR CORRECTION CODE CONTROLLER THEREIN, AND THE METHODS AND SYSTEMS THEREOF

• US 20100162083A1
• Filed: 12/22/2008
• Published: 06/24/2010
• Est. Priority Date: 12/22/2008
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: CHUNG, SHEN MING, CHUNG, YI CHENG
• Granted Patent: US 8,473,815 B2
• Time in Patent Office: Days
• US Class Current: 714/764
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

An ECC controller comprises an ECC encoder, an ECC divider, an ECC constructor and an ECC decoder. The ECC encoder is configured to generate ECC data with different lengths in response to information data to be stored into a flash memory. The ECC divider is configured to divide each ECC datum generated by the ECC encoder into one or more ECC segments according to the length of the ECC datum. The ECC constructor is configured to generate an ECC datum by combining one or more ECC segments for each information datum read from the flash memory. The ECC decoder is configured to correct the errors of the information data read from the flash memory device by using the ECC data generated by the ECC constructor.

Claims

1. A flash memory controller, comprising:

a flash memory interface controller;

a host interface controller;

an error correction code (ECC) encoder configured to receive information data from the host interface controller and generate first ECC data with variable lengths in response to the information data to store in a flash memory;

an ECC divider configured to divide each of the first ECC data into one or more ECC segments according to the length of the first ECC datum and forward the ECC segments to the flash memory interface controller;

an ECC constructor configured to receive one or more of the ECC segments from the flash memory interface controller and generate a second ECC datum by combining the received ECC segments for each of the information data read from the flash memory; and

an ECC decoder configured to correct errors of the information data read from the flash memory based on the information data and the second ECC data and forward the corrected information data to the host interface controller.

2. The flash memory controller of claim 1, wherein each of the information data is stored in a data area of a flash page of a flash block of the flash memory, and the ECC segments are stored in a plurality of spare areas of the flash pages of the flash block of the flash memory.

3. The flash memory controller of claim 2, wherein the one of the ECC segments from one of the first and the second ECC data is stored in the same flash page storing the corresponding information datum.

4. The flash memory controller of claim 3, wherein the remaining ECC segments divided from the first ECC datum are stored in different flash pages of the flash block.

5. The flash memory controller of claim 2, wherein each of the flash pages of the flash memory is configured to store more than one of the ECC segments.

6. The flash memory controller of claim 5, wherein each of the flash pages of the flash memory is configured to store up to two of the ECC segments.

7. The flash memory controller of claim 2, wherein the flash memory interface controller is configured to store pointers along with the ECC segments to the flash memory to indicate the location of the next ECC segment.

8. The flash memory controller of claim 7, wherein the pointer of the last ECC segment of one of the first and the second ECC data points to itself or stores a NULL character.

9. The flash memory controller of claim 2, wherein the flash memory interface controller is configured to store a bitmap to the flash memory recording the usage of the spare areas of the flash pages of one of the flash blocks of the flash memory.

10. The flash memory controller of claim 2, wherein the lengths of the ECC data generated by the ECC encoder are based on the quantity of errors of each flash page storing the corresponding information datum.

11. The flash memory controller of claim 1, wherein the length of each second ECC data is extended when the quantity of errors of the corresponding information datum corrected by the ECC decoder surpasses a threshold value.

20. A flash memory system, comprising:

a flash memory; and

a flash memory controller according to one of the flash memory controllers of claim 1.

12. An error correction code (ECC) controller for a flash memory, comprising:

an ECC encoder configured to generate first ECC data with variable length in response to information data to be stored in a flash memory;

an ECC divider configured to divide each of the first ECC data into one or more ECC segments according to the length of the first ECC datum;

an ECC constructor configured to generate an ECC datum by combining one or more ECC segments for each information datum read from the flash memory; and

an ECC decoder configured to correct the errors of the information data read from the flash memory by using the ECC data generated by the ECC constructor.

13. The ECC controller of claim 12, wherein each of the information data is stored in a data area of a flash page of a flash block of the flash memory, and the ECC segments are stored in a plurality of spare areas of the flash pages of the flash block of the flash memory.

14. The ECC controller of claim 13, wherein the one of the ECC segments from each of the first and the second ECC datum is stored in the same flash page storing the corresponding information datum.

15. The ECC controller of claim 14, wherein the remaining ECC segments divided from the ECC datum are stored in different flash pages of the flash block.

16. The ECC controller of claim 13, wherein each flash page of the flash memory stores more than one of the ECC segments.

17. The ECC controller of claim 16, wherein each of the flash pages of the flash memory is configured to store up to two of the ECC segments.

18. The ECC controller of claim 13, wherein the lengths of the ECC data generated by the ECC encoder are based on the quantity of errors of each flash page storing the corresponding information datum.

19. The ECC controller of claim 12, wherein the length of any of the second ECC datum is extended when the quantity of errors of the corresponding information datum corrected by the ECC decoder surpasses a threshold value.

21. A method for encoding error correction code (ECC) data for information data to be stored in a flash memory, comprising:

generating an ECC datum in response to an information datum to be stored in a flash memory;

dividing the ECC datum into one or more ECC segments;

storing the information datum to a flash page of a flash block of the flash memory; and

storing the ECC segments to a plurality of the flash pages of the flash block of the flash memory.

22. The method of claim 21, which further comprises:

accessing a first ECC portion of the flash page which the information datum is to be stored in;

accessing a next ECC portion linked by the presently accessed ECC portion if the accessed ECC portion is not a last ECC portion of the flash page; and

determining a length of the ECC datum according to the total number of the ECC portions being linked if the accessed ECC portion is the last ECC portion,

wherein each of the ECC portions stores one of the ECC segments.

23. The method of claim 22, wherein each of the ECC portions comprises a pointer field linking to the next ECC portion.

24. The method of claim 22, wherein each of the ECC portions in the same link belongs to different flash pages.

25. The method of claim 22, wherein each of the flash pages comprises a total of two of the ECC portions.

26. The method of claim 21, wherein the ECC segments are stored in the same flash block storing the information datum.

28. The method of claim 26, wherein the combining step comprises:

accessing a first ECC portion of the flash page in which the information datum is stored;

accessing the next ECC portion linked by the presently accessed ECC portion if the accessed ECC portion is not a last ECC portion; and

combining the ECC segments stored in the accessed ECC portions if the accessed ECC portion is the last ECC portion,

wherein each of the ECC portion stores one of the ECC segment.

29. The method of claim 28, wherein each of the ECC portions comprises a pointer field linking to the next ECC portion.

30. The method of claim 28, wherein each of the ECC portions in the same link belongs to different flash pages.

31. The method of claim 28, wherein each of the flash pages comprises a total of two ECC portions.

33. The method of claim 28, which further comprises:

linking another ECC portion to the last ECC portion if the number of corrected errors surpasses a threshold number.

34. The method of claim 28, which further comprises:

updating a bitmap indicating the usage of the ECC portions of the flash block storing the information datum.

27. A method for correcting errors of information data stored in a flash memory, comprising:

reading an information datum stored in a flash memory;

combining one or more ECC segments stored in the flash memory into an ECC datum corresponding to the information datum; and

correcting errors of the information datum by decoding the ECC codeword formed by the information datum and the ECC datum.

32. The method of claim 27, wherein the ECC segments are stored in the same flash block storing the information datum.