Method of detecting data transmission errors in a CAN controller, and a CAN controller for carrying out the method

• US 20100162090A1
• Filed: 01/08/2010
• Published: 06/24/2010
• Est. Priority Date: 10/20/2001
• Status: Active Grant

• Current Assignee: Alexander Springer, Christoph Emde, Johannes Hesselbarth
• Original Assignee: Alexander Springer, Christoph Emde, Johannes Hesselbarth
• Inventors: Hesselbarth, Johannes, Springer, Alexander, Emde, Christoph
• Granted Patent: US 8,799,738 B2
• Time in Patent Office: Days
• US Class Current: 714/807
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration
• CPC Class Codes: H04L 2012/40215 Controller Area Network CAN

Abstract

A method of detecting data transmission errors in a CAN controller includes generating at least one check bit that is verifiable for ensuring the consistency of the transmitted data. A CAN controller that ensures continuous error monitoring during data transmission includes an interface unit for exchanging data with a CAN bus, a memory unit for storing received data and data to be transmitted, and an electronic unit for controlling data transmission between the memory unit and the interface unit. The interface unit of the CAN controller has an arrangement for generating check bits for received data and for verifying check bits for data to be transmitted.

Claims

1. A CAN controller comprising:

an interface unit adapted to exchange data with a CAN bus;

a memory unit adapted to store received data and data to be transmitted; and

an electronic unit to control a data transmission between the memory unit and the interface unit;

wherein the interface unit includes a first arrangement to generate at least one check bit for received data and a second arrangement to verify at least one other check bit for the data to be transmitted.

2. The CAN controller of claim 1, wherein the memory unit includes a RAM chip that includes at least one certain memory area corresponding to each possible item of received data and the data to be transmitted.

3. The CAN controller of claim 1, wherein the electronic unit includes a state machine.

4. The CAN controller of claim 1, further comprising a bus interface having an internal logic that is adapted to transmit the data among the interface unit, the memory unit, the electronic unit, and a microprocessor.

5. A control unit comprising:

a CAN controller including an interface unit to exchange data with a CAN bus, a first memory unit to store received data and data to be transmitted, and an electronic unit to control a data transmission between the memory unit and the interface unit;

a microprocessor; and

a memory device;

wherein the interface unit includes a first arrangement to generate at least one check bit for received data and a second arrangement for verifying the at least one other check bit for the data to be transmitted; and

wherein the microprocessor includes a third arrangement to generate and verify at least one further check bit.

6. The control unit of claim 5, wherein the microprocessor and the CAN controller are integrated into one chip.