SENSOR COMPRISING AT LEAST A VERTICAL DOUBLE JUNCTION PHOTODIODE, BEING INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING INTEGRATION PROCESS

• US 20100163709A1
• Filed: 12/29/2009
• Published: 07/01/2010
• Est. Priority Date: 12/31/2008
• Status: Abandoned Application

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Castagna, Marie Eloisa, Leonardi, Salvatore, Muscara, Anna
• Application Number:
  US12/649,248
• Publication Number:
  US 20100163709A1
• Time in Patent Office: Days
• US Class Current: 250/205
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 31/02165 using interference filters, e.g. multilayer dielectric filters interference filters G02B5/28
• CPC Class Codes: H01L 31/11 characterised by two potential barriers, e.g. bipolar phototransistors
• CPC Class Codes: H05B 47/11 by determining the brightness or colour temperature of ambient light
• CPC Class Codes: Y02B 20/40 Control techniques providing energy savings, e.g. smart controller or presence detection

Abstract

An embodiment relates to a sensor being integrated on a semiconductor substrate and comprising at least a vertical double-junction photodiode, in turn comprising at least one first and one second p-n junction formed in said semiconductor substrate, as well as at least an anti-reflection coating formed on said photodiode. Said at least one anti-reflection coating comprises at least one first and one second different anti-reflection layer being suitable to obtain a responsivity peak in correspondence with a predetermined wavelength of an incident optical signal on said sensor. An embodiment also relates to an integration process of such a sensor, as well as to an ambient light sensor made by means of such a sensor.

Claims

1. A sensor being integrated on a semiconductor substrate and comprising at least one vertical double-junction photodiode, in turn comprising at least one first and one second p-n junction formed in said semiconductor substrate as well as at least one anti-reflection coating formed on said photodiode, said at least one anti-reflection coating comprising at least one first and one second different anti-reflection layer suitable to obtain a responsivity peak in correspondence with a predetermined wavelength of an optical signal being incident on said sensor.

2. A sensor according to claim 1, wherein said responsivity peak corresponds to a human eye sensitivity peak.

3. A sensor according to claim 1, wherein said first anti-reflection layer is formed by a dielectric layer being as thick as half said predetermined wavelength and in that said second anti-reflection layer is formed by a dielectric layer being as thick as a fourth (λ

/4n) of said predetermined wavelength.

4. A sensor according to claim 3, wherein said first anti-reflection dielectric layer is silicon oxide and in that said second anti-reflection dielectric layer is silicon nitride.

5. A sensor according to claim 1, wherein said photodiode is formed in a stacked configuration in said semiconductor substrate having a first doping type by means of a well having a second doping type and an implant formed within said well and having said first doping type, said implant and said well forming said first junction and said well and said semiconductor substrate forming said second junction of said vertical double-junction photodiode.

6. An integration process of a sensor in a multilayer structure comprising a semiconductor substrate and an alternate structure of intermetal dielectric layers, of the type comprising the steps of:

forming in said semiconductor substrate at least one first and one second pn junction, suitable to form at least one vertical double-junction photodiode;

removing said intermetal dielectric layers in correspondence with at least one opening suitable to expose a surface of said semiconductor substrate in correspondence with said double junction,

depositing a first anti-reflection dielectric layer covering at least said surface; and

depositing on said first anti-reflection dielectric layer a second anti-reflection dielectric layer to form a double-layer anti-reflection coating suitable to obtain for the photodiode a responsivity peak in correspondence with a predetermined wavelength of an optical signal being incident on said sensor.

7. An integration process according to claim 6, wherein said deposition step of said first anti-reflection dielectric layer comprises a deposition step of a silicon oxide layer and in that said deposition step of said second anti-reflection layer comprises a deposition step of a silicon nitride layer.

8. An integration process according to claim 6, wherein said step of forming in said semiconductor substrate at least one first and one second pn junction of said photodiode comprises the steps of:

forming in said semiconductor substrate of a first doping type at least one well of a second doping type; and

forming in said well an implant of said first doping type,

said implant and said well forming said first junction and said well and said semiconductor substrate forming said second junction of said photodiode.

9. An integration process according to claim 6, wherein said removal step of said intermetal dielectric layers comprises an etching step using a layer as a stopping layer, said stopping layer completely covering an active area of said sensor above a first dielectric layer, said removal step being suitable to expose a surface of said stopping layer in correspondence with said double junction.

10. An integration process according to claim 9, further comprising a dry etching step of said stopping layer removing it without size losses, and a wet etching step of said first underlying dielectric layer being suitable to expose said surface of said silicon semiconductor substrate in correspondence with said double junction.

11. An electronic device, comprising:

a first p-n junction;

a second p-n junction;

a first antireflective layer disposed over the first and second junctions; and

a second antireflective layer disposed over the first antireflective layer.

12. The electronic device of claim 11 wherein:

the first p-n junction comprises a junction between first layer of a first conductivity disposed over a second layer of a second conductivity; and

the second p-n junction comprises junction between a third layer of the second conductivity disposed over the first layer.

13. The electronic device of claim 11 wherein:

the first p-n junction comprises junction between a first layer of a first level of a first conductivity disposed over a second layer of a second level of a second conductivity; and

the second p-n junction comprises a junction between a third layer of a third level of the second conductivity disposed over the first layer, the third level greater than the first level.

14. The electronic device of claim 11 wherein:

the first p-n junction comprises junction between a first layer of a first level of a first conductivity disposed over a second layer of a second level of a second conductivity; and

the second p-n junction comprises a junction between a third layer of a third level of the second conductivity disposed over the first layer, the third level greater than the first and second levels.

15. The electronic device of claim 11 wherein:

the first p-n junction comprises a junction between a first N-type layer disposed over a second P-type layer; and

the second p-n junction comprises a junction between a third P-type layer disposed over the first layer.

16. The electronic device of claim 11 wherein:

the first p-n junction comprises a junction between first layer of a first conductivity disposed over a substrate of a second conductivity; and

the second p-n junction comprises junction between a second layer of the second conductivity disposed over the first layer.

17. The electronic device of claim 11 wherein:

the first p-n junction comprises a junction between first well of a first conductivity disposed in a substrate of a second conductivity; and

the second p-n junction comprises junction between a second well of the second conductivity disposed in the first well.

18. The electronic device of claim 11, further comprising:

wherein the first p-n junction comprises a junction between first well of a first conductivity disposed in a substrate of a second conductivity;

wherein the second p-n junction comprises junction between a second well of the second conductivity disposed in the first well;

a first electrode in contact with the first well; and

a second electrode in contact with the second well.

19. The electronic device of claim 11, further comprising:

wherein the first p-n junction comprises a junction between first well of a first conductivity disposed in a substrate of a second conductivity;

wherein the second p-n junction comprises junction between a second well of the second conductivity disposed in the first well;

a first electrode in contact with the first well;

a second electrode in contact with the second well; and

a third electrode in contact with the substrate.

20. The electronic device of claim 11 wherein:

the first antireflective layer has a thickness that is approximately equal to one half a wavelength of electromagnetic radiation; and

the second antireflective layer has a thickness that is approximately equal to one fourth of the wavelength.

21. The electronic device of claim 11 wherein:

the first antireflective layer has a thickness that is approximately equal to one half a wavelength of light in a visible portion of the electromagnetic spectrum; and

the second antireflective layer has a thickness that is approximately equal to one fourth of the wavelength.

22. The electronic device of claim 11 wherein:

the first antireflective layer has a thickness that is approximately equal to 270 nanometers; and

the second antireflective layer has a thickness that is approximately equal to 135 nanometers.

23. The electronic device of claim 11 wherein:

the first antireflective layer comprises an oxide; and

the second antireflective layer comprises a nitride.

24. An integrated circuit, comprising:

a first p-n junction;

a second p-n junction;

a first antireflective coating disposed over the first and second junctions; and

a second antireflective coating disposed over the first antireflective coating.

25. The integrated circuit of claim 24, further comprising at least one detector operable to detect a current across at least one of the first and second p-n junctions.

26. The integrated circuit of claim 24, further comprising:

a first detector operable to detect a first current across the first p-n junction;

a second detector operable to detect a second current across the second p-n junction; and

a third detector operable to detect a third current substantially equal to a sum of the first and second currents.

27. The integrated circuit of claim 24, further comprising:

a first detector operable to detect a first current across the first p-n junction;

a second detector operable to detect a second current across the second p-n junction; and

a third detector operable to detect a third current substantially equal to a difference of the first and second currents.

28. The integrated circuit of claim 24, further comprising a protective layer disposed over the second antireflective layer.

29. The integrated circuit of claim 24 wherein:

the first antireflective layer has a thickness that is approximately equal to one half a wavelength of electromagnetic radiation; and

the second antireflective layer has a thickness that is approximately equal to one fourth of the wavelength.

30. A system, comprising:

a first integrated circuit including at least one photodiode each including

a first p-n junction;

a second p-n junction;

a first antireflective coating disposed over the first and second junctions; and

a second antireflective coating disposed over the first antireflective coating; and

a second integrated circuit coupled to the first integrated circuit.

31. The system of claim 30 wherein the first and second integrated circuits are disposed on a same die.

32. The system of claim 30 wherein the first and second integrated circuits are disposed on respective dies.

33. The system of claim 30 wherein the second integrated circuit comprises a controller.

34. The system of claim 30 wherein:

the first antireflective coating has a thickness that is approximately equal to one half a wavelength of electromagnetic radiation; and

the second antireflective coating has a thickness that is approximately equal to one fourth of the wavelength.

35. A method, comprising:

receiving a wavelength of electromagnetic radiation through a first material having a first thickness approximately equal to one fourth of the wavelength and through a second material having a second thickness approximately equal to one half of the wavelength; and

generating a first current across a first p-n junction in response to the received wavelength; and

generating a second current across a second p-n junction in response to the received wavelength.

36. The method of claim 35 wherein the first p-n junction is disposed over the second p-n junction.

37. The method of claim 35 wherein the first material is disposed over the second material.

38. The method of claim 35, further comprising combining the first and second currents.

39. The method of claim 35, further comprising summing the first and second currents.

40. The method of claim 35, further comprising subtracting one of the first and second currents from the other of the first and second currents.

41. The method of claim 35, further comprising adjusting a brightness of an apparatus in response to at least one of the first and second currents.