RADIATION SENSOR WITH PHOTODIODES BEING INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING INTEGRATION PROCESS

• US 20100163759A1
• Filed: 12/29/2009
• Published: 07/01/2010
• Est. Priority Date: 12/31/2008
• Status: Abandoned Application

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Maddiona, Lidia, Leonardi, Salvatore, Abbisso, Salvatore, Castagna, Maria Eloisa
• Application Number:
  US12/649,256
• Publication Number:
  US 20100163759A1
• Time in Patent Office: Days
• US Class Current: 250/552
• CPC Class Codes: G01J 1/0488 with spectral filtering
• CPC Class Codes: G01J 1/4204 with determination of ambient light solar light G01J2001/4266
• CPC Class Codes: G01J 1/4228 arrangements with two or more detectors, e.g. for sensitivity compensation
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 31/02165 using interference filters, e.g. multilayer dielectric filters interference filters G02B5/28
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

An embodiment relates to a sensor integrated on a semiconductor substrate and comprising at least one first and second photodiode including at least one first and one second p-n junction made in such a semiconductor substrate as well as at least one first and one second antireflection coating made on top of such a first and second photodiode. At least one antireflection coating of such a first and second photodiode comprises at least one first and one second different antireflection layer to make a double layer antireflection coating suitable for obtaining for the corresponding photodiode a responsivity peak at a predetermined wavelength of an optical signal incident on the sensor. An embodiment also refers to an integration process of such a sensor, as well as to an ambient light sensor made with such a sensor.

Claims

1. Sensor integrated on a semiconductor substrate and comprising at least one first and one second photodiode including at least one first and one second p-n junction made in said semiconductor substrate as well as at least one first and one second antireflection coating made on top of said first and second photodiodes, wherein at least one antireflection coating of said first and second photodiode comprises at least one first and one second different antireflection layer to make a double layer antireflection coating suitable for obtaining a responsivity peak for the corresponding photodiode at a predetermined wavelength of an optical signal incident on said sensor.

2. Sensor according to claim 1, wherein said responsivity peak corresponds to a sensitivity peak of the human eye.

3. Sensor according to claim 1, wherein said first antireflection layer is made from a dielectric layer of thickness equal to about half of said predetermined wavelength and in that said second antireflection layer is made from a dielectric layer of thickness equal to about a quarter of said predetermined wavelength.

4. Sensor according to claim 3, wherein said first antireflection dielectric layer is silicon oxide and in that said second antireflection dielectric layer is silicon nitride.

5. Sensor according to claim 1, further comprising a circuit integrated in said semiconductor substrate and suitable for connecting said first and second photodiodes, said circuitry subtracting a second electrical signal in output from the second photodiode from a first electrical signal in output from the first photodiode.

6. Sensor according to claim 5, wherein said circuitry comprises at least one first and one second amplification block respectively connected to said first and second photodiodes to suitably weigh said electrical signals through respective weight coefficients before subtracting one from the other so as to obtain said responsivity peak for said sensor at said predetermined wavelength.

7. Sensor according to claim 5, wherein said circuitry also comprises a logic block connected to said first and second amplification blocks and suitable for amplifying and logically processing an output signal from said first and second amplification blocks so as to eliminate a possible negative signal difference obtaining an output signal.

8. Sensor according to claim 5, wherein said circuitry is coated with a metallic layer suitable for protecting it from the incident light.

9. Integration process of a sensor with photodiodes being integrated in a multi-layer structure comprising a semiconductor substrate and a structure of alternating intermetal dielectric layers and metallic layers, as well as an upper passivation layer of the type comprising the steps of:

making at least one first and one second pn junction, suitable for making at least one first and one second photodiode in said semiconductor substrate;

removal of said intermetal dielectric layers and of said upper passivation layer at least one opening suitable for uncovering a surface of said semiconductor substrate at said junctions,

deposition of a first antireflection dielectric layer covering at least said surface; and

deposition on top of said first antireflection dielectric layer of a second antireflection dielectric layer to make a double layer antireflection coating suitable for obtaining a responsivity peak for the corresponding photodiode at a predetermined wavelength of an optical signal incident on said sensor.

10. Integration process according to claim 9, wherein said deposition step of said first antireflection dielectric layer comprises a deposition step of a dielectric layer having a thickness equal to about half of said predetermined wavelength and in that said deposition step of said second antireflection layer comprises a deposition step of a dielectric layer having a thickness equal to about a quarter of said predetermined wavelength.

11. Integration process according to claim 10, wherein said deposition step of said first antireflection dielectric layer comprises a deposition step of a layer of silicon oxide and in that said deposition step of said second antireflection layer comprises a deposition step of a layer of silicon nitride.

12. Integration process according to claim 9, wherein said removal step of said intermetal dielectric layers and of said upper passivation layer comprises an etching selected from a dry, wet or dry, and wet etching.

13. Integration process according to claim 9, wherein said removal step of said intermetal dielectric layers and of said upper passivation layer comprises a combined dry and wet etching to obtain, for said opening, substantially perpendicular walls with respect to said surface of said semiconductor substrate.

14. Integration process according to claim 9, further comprising, after said deposition step of said first antireflection dielectric layer, a removal step by selective etching of said first antireflection dielectric layer for its removal only at one of said junctions, said deposition step of said second antireflection dielectric layer making said double layer antireflection coating only at the other of said junctions.

15. Integration process according to claim 9, wherein said selective etching step of said first antireflection dielectric layer comprises a wet etching step.

16. An electronic device, comprising:

a first p-n junction;

a second p-n junction;

a first antireflective coating disposed over the first junction;

a second antireflective coating disposed over the second junction; and

wherein at least one of the first and second antireflective coatings comprises a first antireflective layer having a first thickness and a second antireflective layer disposed over the first antireflective layer and having a second thickness that is different from the first thickness.

17. The electronic device of claim 16 wherein:

the first p-n junction comprises a junction between first layer of a first conductivity disposed over a second layer of a second conductivity; and

the second p-n junction comprises junction between a third layer of the first conductivity remote from the first layer and disposed over the second layer.

18. The electronic device of claim 16 wherein:

the first p-n junction comprises a junction between a first layer of a first level of a first conductivity disposed over a second layer of a second level of a second conductivity; and

the second p-n junction comprises a junction between a third layer of a third level of the first conductivity disposed over the second layer, the third level greater than the first level.

19. The electronic device of claim 16 wherein:

the first p-n junction comprises a junction between a first layer of a first level of a first conductivity disposed over a second layer of a second level of a second conductivity; and

the second p-n junction comprises a junction between a third layer of a third level of the first conductivity disposed over the second layer, the third level less than the first level.

20. The electronic device of claim 16 wherein:

the first p-n junction comprises a junction between a first layer of a first level of a first conductivity disposed over a second layer of a second level of a second conductivity; and

the second p-n junction comprises a junction between a third layer of a third level of the second conductivity disposed over the second layer, the third level substantially the same as the first level.

21. The electronic device of claim 16 wherein:

the first p-n junction comprises a junction between a first N type layer disposed over a second P type layer; and

the second p-n junction comprises a junction between a third N type layer disposed over the second P type layer.

22. The electronic device of claim 16 wherein:

the first p-n junction comprises a junction between a first layer of a first conductivity disposed over a substrate of a second conductivity; and

the second p-n junction comprises junction between a second layer of the first conductivity disposed over the substrate.

23. The electronic device of claim 16, further comprising:

wherein the first p-n junction comprises a junction between first layer of a first conductivity disposed over a second layer of a second conductivity;

wherein the second p-n junction comprises junction between a third layer of the first conductivity remote from the first layer and disposed over the second layer;

a first electrode in contact with the first layer; and

a second electrode in contact with the third layer.

24. The electronic device of claim 16, further comprising:

wherein the first p-n junction comprises a junction between first layer of a first conductivity disposed over a second layer of a second conductivity;

wherein the second p-n junction comprises junction between a third layer of the first conductivity remote from the first layer and disposed over the second layer;

a first electrode in contact with the first layer;

a second electrode in contact with the second layer; and

a third electrode in contact with the third layer.

25. The electronic device of claim 16 wherein:

the first thickness is approximately equal to one half a wavelength of electromagnetic radiation; and

the second thickness is approximately equal to one fourth of the wavelength.

26. The electronic device of claim 16 wherein:

the first thickness is approximately equal to one half a wavelength of light in a visible portion of the electromagnetic spectrum; and

the second thickness is approximately equal to one fourth of the wavelength.

27. The electronic device of claim 16 wherein:

the first thickness is approximately equal to 270 nanometers; and

the second thickness is approximately equal to 135 nanometers.

28. The electronic device of claim 16 wherein:

the first thickness is approximately equal to 190 nanometers; and

the second thickness is approximately equal to 70 nanometers.

29. The electronic device of claim 16 wherein:

the first antireflective layer comprises an oxide; and

the second antireflective layer comprises a nitride.

30. The electronic device of claim 16, further comprising an insulator disposed between the first and second junctions.

31. The electronic device of claim 16 wherein the first thickness is greater than the second thickness.

32. An integrated circuit, comprising:

a first p-n junction;

a second p-n junction;

a first antireflective coating disposed over the first junction;

a second antireflective coating disposed over the second junction; and

wherein at least one of the first and second antireflective coatings comprises a first antireflective layer having a first thickness and a second antireflective layer disposed over the first antireflective layer and having a second thickness that is different from the first thickness.

33. The integrated circuit of claim 32, further comprising a protective layer disposed over the second antireflective layer.

34. The integrated circuit of claim 32 wherein:

the first antireflective layer has a thickness that is approximately equal to one half a wavelength of electromagnetic radiation; and

the second antireflective layer has a thickness that is approximately equal to one fourth of the wavelength.

35. The integrated circuit of claim 32, further comprising:

a first amplifier operable to amplify a first signal generated by the first p-n junction with a first gain;

a second amplifier operable to amplify a second signal generated by the second p-n junction with a second gain; and

a combiner operable to combine the amplified first and second signals to generate a combined signal.

36. The integrated circuit of claim 32, further comprising:

a first amplifier operable to amplify a first signal generated by the first p-n junction with a first gain;

a second amplifier operable to amplify a second signal generated by the second p-n junction with a second gain;

a combiner operable to combine the amplified first and second signals to generate a combined signal; and

a third amplifier operable to amplify the combined signal.

37. The integrated circuit of claim 32, further comprising:

a first amplifier operable to amplify a first signal generated by the first p-n junction with a first gain;

a second amplifier operable to amplify a second signal generated by the second p-n junction with a second gain;

a combiner operable to combine the amplified first and second signals to generate a combined signal; and

a third amplifier operable to amplify the combined signal such that the amplified combined signal has nonzero values only of a single polarity.

38. The integrated circuit of claim 32, further comprising:

a first amplifier operable to amplify a first signal generated by the first p-n junction with a first gain;

a second amplifier operable to amplify a second signal generated by the second p-n junction with a second gain; and

a combiner operable to subtract one of the amplified first and second signals from the other of the first and second amplified signals to generate a combined signal.

39. The integrated circuit of claim 32, further comprising:

a first current mirror operable to amplify a first current generated by the first p-n junction with a first gain and to provide the amplified first current to a node in a first direction; and

a second current mirror operable to amplify a second current generated by the second p-n junction with a second gain and to provide the amplified second current to the node in a second direction to generate a combined current signal at the node.

40. The integrated circuit of claim 32, further comprising:

a first current mirror operable to amplify a first current generated by the first p-n junction with a first gain and to provide the amplified first current to a node in a first direction; and

a second current mirror operable to amplify a second current generated by the second p-n junction with a second gain and to provide the amplified second current to the node in a second direction to generate a combined current signal at the node, the combined current representing a light response that is similar to a light response of a human eye.

41. The integrated circuit of claim 32, further comprising:

a first current mirror operable to amplify a first current generated by the first p-n junction with a first gain and to provide the amplified first current to a node in a first direction;

a second current mirror operable to amplify a second current generated by the second p-n junction with a second gain and to provide the amplified second current to the node in a second direction to generate a combined current signal at the node; and

a polarity circuit operable to cause the combined current to have nonzero values only of a single polarity.

42. A system, comprising:

a first integrated circuit including;

at least a first photodiode including a first p-n junction and a first antireflective coating disposed over the first junction,

at least a second photodiode including a second p-n junction and a second antireflective coating disposed over the second junction, and

wherein at least one of the first and second antireflective coatings comprises a first antireflective layer having a first thickness and a second antireflective layer disposed over the first antireflective layer and having a second thickness that is different from the first thickness; and

a second integrated circuit coupled to the first integrated circuit.

43. The system of claim 42 wherein the first and second integrated circuits are disposed on a same die.

44. The system of claim 42 wherein the first and second integrated circuits are disposed on respective dies.

45. The system of claim 42 wherein the second integrated circuit comprises a controller.

46. The system of claim 42 wherein:

the first antireflective layer has a thickness that is approximately equal to one half a wavelength of electromagnetic radiation; and

the second antireflective layer has a thickness that is approximately equal to one fourth of the wavelength.

47. The system of claim 42 wherein:

the first integrated circuit comprises

a first amplifier operable to amplify a first signal generated by the first p-n junction with a first gain, and

a second amplifier operable to amplify a second signal generated by the second p-n junction with a second gain; and

the second integrated circuit is operable to adjust ambient lighting in response to at least one of the first and second signals.

48. A method, comprising:

receiving a first wavelength of electromagnetic radiation through a first antireflective layer having a first thickness and through a second antireflective layer having a second thickness that is different than the first thickness;

receiving a second wavelength of electromagnetic radiation through a third antireflective layer;

generating a first signal across a first p-n junction in response to the received first wavelength; and

generating a second signal across a second p-n junction in response to the received second wavelength.

49. The method of claim 48 wherein the first thickness is less than the second thickness.

50. The method of claim 48 wherein:

the first thickness is approximately equal to one fourth of the first wavelength; and

the second thickness is approximately equal to one half of the second wavelength.

51. The method of claim 48 wherein the third antireflective layer has a third thickness that is approximately the same as the first thickness.

52. The method of claim 48, further comprising controlling a brightness level in response to a combination of the first and second signals.

53. The method of claim 48, further comprising controlling a brightness level in response to a difference between the first and second signals.

54. The method of claim 48, further comprising combining the first and second signals such that no value of the combined signal has particular polarity.

55. The method of claim 48, further comprising:

wherein the first signal comprises a first current;

wherein the second signal comprises a second current;

sinking a third current derived from one of the first and second currents to a node; and

sourcing a fourth current derived from the other of the first and second currents to the node.

56. The method of claim 55 wherein:

the third current is equal to the one of the first and second currents; and

the fourth current is equal to the other of the first and second currents.

57. The method of claim 55 wherein the first wavelength equals the second wavelength.