Multiple-Gate Transistors with Reverse T-Shaped Fins

• US 20100163842A1
• Filed: 12/29/2008
• Published: 07/01/2010
• Est. Priority Date: 12/29/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lai, Li-Shyue, Lin, Jing-Cheng
• Granted Patent: US 8,058,692 B2
• Time in Patent Office: Days
• US Class Current: 257/19
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

Claims

1. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate;

forming a first insulation region and a second insulation region in the semiconductor substrate and facing each other;

forming an epitaxial semiconductor region having a reversed T-shape and comprising;

a horizontal plate comprising a bottom portion between and adjoining the first insulation region and the second insulation region, wherein a bottom surface of the horizontal plate contacts the semiconductor substrate; and

a fin over and adjoining the horizontal plate;

forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and

forming a gate electrode over the gate dielectric.

2. The method of claim 1, wherein the horizontal plate and the fin comprise germanium, and wherein the semiconductor substrate is a silicon substrate.

3. The method of claim 1, wherein the step of forming the epitaxial semiconductor region comprises:

epitaxially growing a first germanium-containing region over and contacting the semiconductor substrate; and

epitaxially growing a second germanium-containing region having a different composition than the first germanium-containing region over the first germanium-containing region.

4. The method of claim 3, wherein the first germanium-containing region is formed of silicon germanium, and wherein the second germanium-containing region is formed of substantially pure germanium.

5. The method of claim 3, wherein the first germanium-containing region comprises a superlattice structure comprising alternating germanium layers and silicon germanium layers, and wherein the second germanium-containing region is formed of substantially pure germanium.

6. The method of claim 1, wherein the step of forming the epitaxial semiconductor region comprises:

etching a portion of the semiconductor substrate between the first insulation region and the second insulation region to form a recess, wherein the recess has a bottom no lower than a bottom surface of the first insulation region and lower than a top surface of the first insulation region, and wherein a first sidewall of the first insulation region and a second sidewall of the second insulation region facing the first sidewall are exposed;

epitaxially growing a germanium-containing material in the recess; and

patterning an upper portion of the germanium-containing material to form the fin, wherein a lower portion of the germanium-containing material is not etched and forms the horizontal plate.

7. The method of claim 6 further comprising, during the step of patterning the upper portion of the germanium-containing material, simultaneously etching portions of the first insulation region and the second insulation region adjoining the upper portion of the germanium-containing material.

8. The method of claim 7 further comprising, after the step of patterning the upper portion of the germanium-containing material, forming a dielectric layer over the horizontal plate, the first insulation region, and the second insulation region, wherein a top portion of the fin is exposed through the dielectric layer.

9. The method of claim 6, wherein when the step of patterning the upper portion of the germanium-containing material is performed, the first insulation region and the second insulation region are not etched.

10. The method of claim 9 further comprising etching top portions of each of the first insulation region and the second insulation region until recessed portions of the first insulation region and the second insulation region have top surfaces lower than a top surface of the horizontal plate and higher than a bottom surface of the horizontal plate.

11. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate;

forming a first shallow trench isolation (STI) region and a second STI region in the semiconductor substrate, wherein the semiconductor substrate comprises a portion horizontally between and adjoining the first STI region and the second STI region;

etching the portion of the semiconductor substrate to form a recess, wherein the recess has a bottom lower than a top surface of the first STI region and no lower than a bottom surface of the first STI region, and wherein sidewalls of the first STI region and the second STI regions are exposed through the recess;

epitaxially growing a germanium-containing region in the recess;

etching only an upper portion of the germanium-containing region, so that remaining portions of the germanium-containing region have a reversed T-shape comprising a horizontal plate and a fin over the horizontal plate;

forming a gate dielectric on a top surface and covering at least top portions of sidewalls of the fin; and

forming a gate electrode over the gate dielectric.

12. The method of claim 11 further comprising, after the step of etching the germanium-containing region and before the step of forming the gate dielectric, forming a dielectric layer covering the horizontal plate, wherein a top portion of the fin are not covered by the dielectric layer.

13. The method of claim 11, wherein the horizontal plate comprises silicon germanium, and wherein a top portion of the fin is formed of substantially pure germanium.

14. The method of claim 11, wherein the horizontal plate comprises a superlattice structure comprising alternating germanium layers and silicon germanium layers, and wherein a top portion of the fin is formed of substantially pure germanium.

15. The method of claim 11, wherein during the step of etching only the upper portion of the germanium-containing region, simultaneously removing top portions of the first STI region and the second STI region adjoining the portion of the semiconductor substrate.

16. The method of claim 11 further comprising removing top portions of the first STI region and the second STI region adjoining the portion of the semiconductor substrate so that remaining portions of the first STI region and the second STI region have top surfaces lower than a top surface of the horizontal plate and higher than a bottom surface of the horizontal plate.

17. An integrated circuit structure comprising:

a semiconductor substrate;

a first insulation region and a second insulation region in the semiconductor substrate; and

an epitaxial region having a reversed T-shape and comprising;

a horizontal plate between and adjoining the first insulation region and the second insulation region, wherein a bottom of the horizontal plate contacts the semiconductor substrate, and wherein the bottom is no lower than a bottom surface of the first insulation region; and

a fin over and adjoining the horizontal plate;

a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and

a gate electrode over the gate dielectric.

18. The integrated circuit structure of claim 17, wherein the semiconductor substrate comprises substantially pure silicon, and the epitaxial region comprises germanium.

19. The integrated circuit structure of claim 17, wherein the horizontal plate comprises silicon germanium, and wherein a top portion the fin is formed of substantially pure germanium.

20. The integrated circuit structure of claim 17, wherein the horizontal plate comprises a superlattice structure comprising a plurality of germanium layers and a plurality of silicon germanium layers stacked in an alternating pattern.

21. The integrated circuit structure of claim 17, wherein top surfaces of the first insulation region and the second insulation region comprise first portions level with a top surface of the horizontal plate.

22. The integrated circuit structure of claim 21 further comprising a third insulation region in the semiconductor substrate and separated from the first insulation region and the second insulation region, wherein the third insulation region comprises a bottom surface substantially level with a bottom surface of the first insulation region and a top surface higher than the top surface of the horizontal plate.

23. The integrated circuit structure of claim 21, wherein the top surfaces of the first insulation region and the second insulation region further comprise second portions higher than the first portions, and wherein the second portions are farther away from the horizontal plate than the first portions.

24. The integrated circuit structure of claim 21 further comprising a dielectric layer over the horizontal plate, the first insulation region, and the second insulation region, wherein a top portion of the fin is not covered by the dielectric layer.

25. The integrated circuit structure of claim 17, wherein a top surface of the fin is substantially level with portions of top surfaces of the first insulation region and the second insulation region, and wherein a top surface of the horizontal plate is lower than the portions of the top surfaces of the first insulation region and the second insulation region.

26. The integrated circuit structure of claim 25, wherein the top surfaces of the first insulation region and the second insulation region further comprise second portions higher than the first portions.

27. The integrated circuit structure of claim 17, wherein first portions of top surfaces of the first insulation region and the second insulation region are lower than a top surface of the horizontal plate, and higher than a bottom surface of the horizontal plate.

28. The integrated circuit structure of claim 27, wherein the top surfaces of the first insulation region and the second insulation region further comprise second portions higher than the first portions.

29. An integrated circuit structure comprising:

a semiconductor substrate;

a first shallow trench isolation (STI) region and a second STI region in the semiconductor substrate;

a germanium-containing region having a reversed T-shape and comprising;

a horizontal plate between and adjoining the first STI region and the second STI region, wherein a bottom of the horizontal plate contacts the semiconductor substrate and is no lower than a bottom surface of the first STI region; and

a fin over and adjoining the horizontal plate;

a gate dielectric on a top surface and top portions of sidewalls of the fin; and

a gate electrode over the gate dielectric.

30. The integrated circuit structure of claim 29 further comprising a dielectric layer covering the horizontal plate and vertically between the gate dielectric and the horizontal plate.

31. The integrated circuit structure of claim 29, wherein the horizontal plate comprises silicon germanium, and wherein a top portion of the fin is formed of substantially pure germanium.

32. The integrated circuit structure of claim 29, wherein the horizontal plate comprises a superlattice structure comprising alternating germanium layers and silicon germanium layers, and wherein a top portion of the fin is formed of substantially pure germanium.

33. The integrated circuit structure of claim 29, wherein top surfaces of the first STI region and the second STI region are level with a top surface of the horizontal plate, and wherein the integrated circuit structure further comprises a third STI region having a top surface substantially level with a top surface of the fin.

34. The integrated circuit structure of claim 29, wherein top surfaces of the first STI region and the second STI region comprise portions lower than a top surface of the horizontal plate and higher than a bottom surface of the horizontal plate.

35. The integrated circuit structure of claim 34 further comprising a third STI region having a top surface higher than the top surface of the horizontal plate.