QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS

• US 20100163847A1
• Filed: 12/31/2008
• Published: 07/01/2010
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hudait, Mantu K., Radosavljevic, Marko, Kavalieros, Jack T., Dewey, Gilbert, Rakshit, Titash, Pillarisetty, Ravi, Majhi, Prashant, Tsai, Willman
• Granted Patent: US 7,759,142 B1
• Time in Patent Office: Days
• US Class Current: 257/24
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/802 with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors H01L29/806 takes precedence; with one dimensional electron gas H01L29/775; with dimensional electron gas H01L29/778

Abstract

Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Claims

1. A method comprising:

removing a first portion of a top barrier layer and of a channel layer of a quantum well in a substrate to form a first junction region and a different second portion of the top barrier layer and a channel layer to form a second junction region in the substrate; and

forming a thickness of a junction material in the first junction region and in the second junction region;

wherein the junction material has a lattice spacing different than a lattice spacing of a channel material of the channel layer and causes a uni-axial strain in a third portion of the channel layer between the first and second junction regions.

2. The method of claim 1, wherein the channel layer is between a top barrier layer and a bottom buffer layer of the quantum well, and wherein the top barrier layer and the bottom buffer layer each comprise a material having a lattice spacing different than a lattice spacing of the channel material and each cause a bi-axial strain in the third portion of the channel layer, in addition to the uni-axial strain.

3. The method of claim 2, wherein removing the first and second portion further comprises removing a first and second portion of an interlayer dielectric (ILD) layer to form a contact opening through the ILD layer, and into, but not through the channel layer.

4. The method of claim 2, wherein removing the first and second portion comprises using an anisotropic dry etch to form two contact openings, each opening extending through a thickness of but not completely through the channel layer;

and further comprising;

expanding the contact openings in the channel layer but not in the top barrier layer using a selective isotropic wet etch to extend the openings completely through the channel layer and to expose a bottom buffer layer of the quantum well.

5. The method of claim 4, wherein removing comprises removing a first thickness of, but not removing a remaining thickness of the channel layer, and wherein expanding comprises removing the remaining thickness and widening the openings in the channel layer to a width wider than a width of the openings in the ILD layer.

6. The method of claim 4, wherein forming comprising forming a metal material on the channel material in the expanded contact openings, but not on a barrier material of the top barrier layer.

7. The method of claim 6, further comprising thermally treating the metal material to form an alloy material including the metal material and the channel material at an interface between the metal material and the channel material.

8. The method of claim 7, wherein forming comprises depositing a Nickel (Ni) material using one of atomic layer deposition (ALD) and physical vapor deposition (PVD);

wherein the channel material comprises germanium (Ge);

wherein the top barrier and bottom buffer layer comprise silicon; and

wherein the uni-axial strain and the bi-axial strains are compressive strains.

9. The method of claim 7, wherein thermally treating comprises annealing the interface to form an alloy material between the top barrier layer, the bottom buffer layer, the channel layer and the metal material.

10. The method of claim 2, wherein removing a first and second portion comprises:

removing a first portion of a top barrier layer and of the channel layer to expose a bottom buffer layer of the quantum well, and removing a different second portion of the top barrier layer and of the channel layer to expose the bottom buffer layer of the quantum well.

11. The method of claim 10, wherein removing comprises forming a first sidewall of the barrier layer and channel layer and a first bottom surface on the bottom buffer layer in the first junction region, and forming a second sidewall of the barrier layer and channel layer and a second bottom surface on the bottom buffer layer in the second junction region.

12. The method of claim 11, wherein forming comprises epitaxially regrowing the channel material in the junction regions.

13. The method of claim 12, wherein forming comprises forming a graded conformal material, of the same material as the channel material, on the sidewall and bottom surfaces.

14. The method of claim 13, wherein forming comprising forming the junction material at a temperature less than or equal to 550 degrees Celsius, and causing the uni-axial strain prior to annealing.

15. The method of claim 10, wherein removing the first and second portion further comprises forming a gate dielectric layer over the top barrier layer, dry etching the gate dielectric layer to form a mask over a third portion of the top barrier layer and of the channel layer, using a first wet selective etch to remove the first and second portion of the top barrier layer, and using a second selective wet etch to remove the first and second portion of the channel layer.

16. The method of claim 13, wherein the channel material comprises in an Indium Gallium Arsenide (InGaAs) material;

and wherein forming comprises growing an InGaAs material having a higher concentration of Indium than a concentration of Indium of the channel material.

17. The method of claim 16, wherein the top barrier material comprises Indium Phosphorus, the bottom buffer layer comprises Indium Aluminum Arsenic;

and wherein the uni-axial strain and the bi-axial strains are compressive strains.

18. A transistor comprising:

a quantum well in a substrate, the quantum well comprising a channel layer between a top barrier layer and a bottom buffer layer, wherein the top barrier layer and the bottom buffer layer each comprise a material having a lattice spacing different than a lattice spacing of a channel material of the channel layer and each causing a bi-axial strain in the channel layer;

a first junction region adjacent to the quantum well, the first junction region through the channel layer, and to the bottom buffer layer;

a different second junction region adjacent to the quantum well, the second junction region through the channel layer, and to the bottom buffer layer;

a junction material in the first junction region and in the second junction region having a lattice spacing different than a lattice spacing of the channel material, and causing a uni-axial strain in the channel layer, in addition to the bi-axial strain.

19. The transistor of claim 18, wherein the junction material comprises an alloy material at an interface between the channel layer and a metal material, and wherein the alloy comprises the channel material and the metal.

20. The transistor of claim 19, wherein the metal comprises Nickel (Ni);

wherein the channel material comprises germanium (Ge);

wherein the top barrier and bottom buffer layer comprise silicon; and

wherein the uni-axial strain and the bi-axial strains are compressive strains.

21. The transistor of claim 18, wherein the junction material comprises a graded material of the same material as the channel material on sidewall surfaces of the top barrier layer and channel layer, and on top surfaces of the bottom buffer layer.

22. The transistor of claim 21, wherein the channel material comprises Indium Gallium Arsenide (InGaAs);

wherein the junction material comprises InGaAs material having a higher concentration of Indium than a concentration of Indium of the channel material;

wherein the top barrier material comprises Indium Phosphide (InP);

wherein the bottom buffer layer comprises Indium Aluminum Arsenide (InAlAs); and

wherein the uni-axial strain and the bi-axial strains are compressive strains.

23. An apparatus comprising:

a transistor quantum well in a substrate, the quantum well comprising a channel layer between a top barrier layer and a bottom buffer layer, wherein the top barrier layer and the bottom buffer layer each comprise a material having a lattice spacing smaller than a lattice spacing of a channel material of the channel layer to each cause a bi-axial compressive strain in the channel layer;

a first junction region adjacent to a portion of the quantum well, the first junction region extending through the top barrier layer, through the channel layer, and to the bottom buffer layer;

a different second junction region adjacent to the portion of the quantum well, the second junction region extending through the top barrier layer, through the channel layer, and to the bottom buffer layer;

a junction material in the first junction region and in the second junction region, the junction material having a lattice spacing greater than a lattice spacing of the channel material to cause a uni-axial compressive strain in the channel layer, in addition to the bi-axial compressive strain.