SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME

• US 20100163867A1
• Filed: 12/22/2009
• Published: 07/01/2010
• Est. Priority Date: 12/26/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, SAKATA, Junichiro
• Granted Patent: US 8,330,156 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

In a thin film transistor including an oxide semiconductor, an oxide cluster having higher electrical conductance than the oxide semiconductor layer is formed between the oxide semiconductor layer and a gate insulating layer, whereby field effect mobility of the thin film transistor can be increased and increase of off current can be suppressed.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a plurality of oxide clusters over the gate insulating layer;

an oxide semiconductor layer over the gate insulating layer and the plurality of oxide clusters; and

source and drain electrode layers over the oxide semiconductor layer,

wherein the plurality of oxide clusters have electrical conductivity,

wherein the oxide semiconductor layer and the source electrode layer are electrically connected to each other, and

wherein the oxide semiconductor layer and the drain electrode layer are electrically connected to each other.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes at least one of indium, gallium, and zinc.

3. The semiconductor device according to claim 1, wherein the plurality of oxide clusters include at least one of indium, zinc, tin, molybdenum, and tungsten.

4. The semiconductor device according to claim 1, wherein the plurality of oxide clusters include at least one of indium oxide, zinc oxide, indium tin oxide, indium zinc oxide, molybdenum oxide, and tungsten oxide.

5. The semiconductor device according to claim 1, wherein electrical conductance of the plurality of oxide clusters is higher than electrical conductance of the oxide semiconductor layer.

6. The semiconductor device according to claim 1, wherein a film thickness of the oxide semiconductor layer is equal to or greater than 30 nm and equal to or less than 100 nm.

7. The semiconductor device according to claim 1, wherein a height of the plurality of oxide clusters from a reference surface in contact with the gate insulating layer is equal to or greater than 3 nm and equal to or less than 5 nm.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor layer has a region which is between the source and drain electrode layers and whose thickness is smaller than a thickness of a region overlapping with the source and drain electrode layers.

9. The semiconductor device according to claim 1, wherein a channel protective layer including an inorganic material is formed over the oxide semiconductor layer.

25. An electronic device having the semiconductor device according to claim 1.

10. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a plurality of oxide clusters over the gate insulating layer;

an oxide semiconductor layer over the gate insulating layer and the plurality of oxide clusters;

a buffer layer having n-type electrical conductivity over the oxide semiconductor layer; and

source and drain electrode layers over the buffer layer,

wherein the plurality of oxide clusters have electrical conductivity,

wherein a carrier concentration of the buffer layer is higher than a carrier concentration of the oxide semiconductor layer,

wherein the oxide semiconductor layer and the source electrode layer are electrically connected to each other with the buffer layer interposed therebetween, and

wherein the oxide semiconductor layer and the drain electrode layer are electrically connected to each other with the buffer layer interposed therebetween.

11. The semiconductor device according to claim 10, wherein the oxide semiconductor layer and the buffer layer include at least one of indium, gallium, and zinc.

12. The semiconductor device according to claim 10, wherein the plurality of oxide clusters include at least one of indium, zinc, tin, molybdenum, and tungsten.

13. The semiconductor device according to claim 12, wherein the plurality of oxide clusters include at least one of indium oxide, zinc oxide, indium tin oxide, indium zinc oxide, molybdenum oxide, and tungsten oxide.

14. The semiconductor device according to claim 10, wherein electrical conductance of the plurality of oxide clusters is higher than electrical conductance of the oxide semiconductor layer.

15. The semiconductor device according to claim 10, wherein a film thickness of the oxide semiconductor layer is equal to or greater than 30 nm and equal to or less than 100 nm.

16. The semiconductor device according to claim 10, wherein a height of the plurality of oxide clusters from a reference surface in contact with the gate insulating layer is equal to or greater than 3 nm and equal to or less than 5 nm.

17. The semiconductor device according to claim 10, wherein the oxide semiconductor layer has a region which is between the source and drain electrode layers and whose thickness is smaller than a thickness of a region overlapping with the source and drain electrode layers.

18. The semiconductor device according to claim 10, wherein a channel protective layer including an inorganic material is formed over the oxide semiconductor layer.

26. An electronic device having the semiconductor device according to claim 10.

19. A method for manufacturing a semiconductor device comprising:

forming a gate electrode layer over a substrate;

forming a gate insulating layer over the gate electrode layer;

forming a plurality of oxide clusters having electrical conductivity over the gate insulating layer in a dispersed manner;

forming an oxide semiconductor film over the gate insulating layer and the plurality of oxide clusters by a sputtering method;

forming an island-like second oxide semiconductor film with an etching method of the oxide semiconductor film;

forming a conductive layer over the island-like second oxide semiconductor film; and

forming an oxide semiconductor layer and source and drain electrode layers with an etching method of the island-like second oxide semiconductor film and the conductive layer.

20. The method for manufacturing a semiconductor device according to claim 19, wherein the oxide semiconductor film includes at least one of indium, gallium, and zinc.

21. The method for manufacturing a semiconductor device according to claim 19, wherein the plurality of oxide clusters includes at least one of indium, zinc, tin, molybdenum, and tungsten.

22. The method for manufacturing a semiconductor device according to claim 19, wherein electrical conductance of the plurality of oxide clusters is made higher than electrical conductance of the oxide semiconductor layer.

23. The method for manufacturing a semiconductor device according to claim 19, wherein the plurality of oxide clusters are formed by a sputtering method so as to have a height of equal to or greater than 3 nm and equal to or less than 5 nm from a reference surface in contact with the gate insulating layer.

24. The method for manufacturing a semiconductor device according to claim 19, wherein the oxide semiconductor layer has a region which is between the source and drain electrode layers and whose thickness is smaller than a thickness of a region overlapping with the source and drain electrode layers.