SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

• US 20100163930A1
• Filed: 12/18/2009
• Published: 07/01/2010
• Est. Priority Date: 12/26/2008
• Status: Active Grant

• Current Assignee: Sanken Electric Company Limited
• Original Assignee: Sanken Electric Company Limited
• Inventors: Kaneko, Nobuo
• Granted Patent: US 8,164,118 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

An object of the present invention is to reduce on-state resistance and increases reliability in a semiconductor device having an electrode formed in a recessed structure.

As illustrated in FIG. 1B, a first insulating layer 103 is formed. Then, as illustrated in FIG. 1C, a photolithography process is carried out to form a photoresist pattern 104. Subsequently, as illustrated in FIG. 1D, dry etching is applied to the first insulating layer 103. Then, as illustrated in FIG. 1E, a laminated semiconductor structure is etched. Next, in this state, wet etching is applied to the first insulating layer 103 as illustrated in FIG. 1F. Next, in this state, an electrode material 105 is formed on the entire exposed surface as illustrated in FIG. 1G. Finally, as illustrated in 1H, the photoresist pattern 104 is removed.

Claims

1. A semiconductor device manufacturing method forming an electrode in a recessed structure formed in a semiconductor layer, comprising:

a first insulating layer formation process, forming a first insulating layer on the surface of the semiconductor layer;

a lithography process, forming a photoresist pattern having an opening on the first insulating layer;

a semiconductor etching process, etching the semiconductor layer using the photoresist pattern and first insulating layer as a mask to form the recessed structure in the opening;

an electrode film formation process, forming a film of an electrode material; and

a lift-off process, removing the photoresist pattern to pattern the electrode material so as to form the electrode, wherein

an insulating layer side etching process, making an wider opening of the first insulating layer than the opening of the photoresist where the opening of the photoresist is formed, is performed between the lithography process and the electrode film formation process.

2. The semiconductor device manufacturing method according to claim 1, further comprising, an insulating layer etching process, etching the first insulating layer using a dry etching method, between the lithography process and the semiconductor etching process,

wherein

the insulating layer side etching process is performed between the semiconductor etching process and the electrode film formation process.

3. The semiconductor device manufacturing method according to claim 1, wherein

the insulating layer side etching process is performed between the lithography process and the semiconductor etching process.

4. The semiconductor device manufacturing method according to claim 1, wherein

the insulating layer side etching process is performed, so that the first insulating layer is etched by a wet etching method.

5. The semiconductor device manufacturing method according to claim 1, further comprising, a cleaning process, cleaning the semiconductor layer in the recessed structure, between the semiconductor etching process and the electrode film formation process.

6. The semiconductor device manufacturing method according to claim 1, further comprising, a second insulating layer formation process, forming a second insulating layer on the electrode after the lift-off process.

7. The semiconductor device manufacturing method according to claim 6, wherein

thermal treatment is performed after the second insulating layer formation process.

8. The semiconductor device manufacturing method according to claim 1, wherein

in the electrode film formation process, the film of the electrode material is formed by an evaporation method.

9. The semiconductor device manufacturing method according to claim 1, wherein

the semiconductor layer has a laminated structure, and

the electrode is connected to the interface in the laminated structure.

10. A semiconductor device in which an electrode is embedded in a recessed structure formed in a semiconductor layer, wherein

the electrode includes:

a bottom surface portion contacting the bottom surface of the recessed structure;

a side surface portion contacting the side surface of the recessed structure;

an upper surface portion having a flat portion opposed to the bottom surface portion and existing at the upper side; and

a tapered portion extending from the periphery of the upper surface portion toward the upper surface of the semiconductor layer, in which the height of surface of the electrode becomes lower toward the outer periphery.

11. The semiconductor device according to claim 10, wherein

the semiconductor layer has a laminated structure including a channel layer in which a two-dimensional electron gas is formed and a carrier supply layer having a lattice constant smaller than that of the channel layer.

12. The semiconductor device according to claim 11, wherein

the electrode is used for electrical contact to the two-dimensional electron gas.

13. The semiconductor device according to claim 11, wherein

the bottom surface portion is formed in the channel layer.

14. The semiconductor device according to claim 10, wherein

the angle between the side surface portion and bottom surface portion is substantially vertical.

15. The semiconductor device according to claim 10, wherein

the taper angle between the side surface portion and bottom surface portion is in the range of 20°

to 80°

.

16. The semiconductor device according to claim 10, wherein

the tapered portion lies adjacent to the side surface portion and upper surface portion.

17. The semiconductor device according to claim 10, wherein

the thickness of the electrode becomes maximum at the flat portion.