Power Device with Monolithically Integrated RC Snubber

• US 20100163950A1
• Filed: 06/25/2009
• Published: 07/01/2010
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Black, Arthur, Gladish, Jon
• Granted Patent: US 8,829,624 B2
• Time in Patent Office: Days
• US Class Current: 257/302
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7817 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit

Abstract

A semiconductor structure includes a power transistor monolithically integrated with a RC snubber in a die. The power transistor includes body regions extending in a silicon region, gate electrodes insulated from the body region by a gate dielectric, source regions extending in the body regions, the source and the body regions being of opposite conductivity type, and a source interconnect contacting the source regions. The RC snubber comprises including snubber electrodes insulated from the silicon region by a snubber dielectric such that the snubber electrodes and the silicon region form a snubber capacitor having a predetermined value. The snubber electrodes are connected to the source interconnect in a manner so as to form a snubber resistor of a predetermined value between the snubber capacitor and the source interconnect. The snubber capacitor and the snubber resistor are configured to substantially dampen output ringing when the power transistor switches states.

Claims

1. A semiconductor structure comprising:

a power transistor monolithically integrated with a RC snubber in a die, wherein;

(a) the power transistor comprises;

body regions extending in a silicon region;

gate electrodes insulated from the body region by a gate dielectric;

source regions extending in the body regions, the source and the body regions being of opposite conductivity type;

a source interconnect contacting the source regions;

(b) the RC snubber comprises;

snubber electrodes insulated from the silicon region by a snubber dielectric such that the snubber electrodes and the silicon region form a snubber capacitor having a predetermined value, the snubber electrodes being connected to the source interconnect in a manner so as to form a snubber resistor of a predetermined value between the snubber capacitor and the source interconnect,

wherein the snubber capacitor and the snubber resistor are configured to substantially dampen output ringing when the power transistor switches states.

2. The semiconductor structure of claim 1 further comprising a plurality of gate trenches each including a gate electrode, and a plurality of snubber trenches each including a snubber electrode.

3. The semiconductor structure of claim 2 wherein the snubber trenches and gate trenches extend parallel to each other along rows, the structure further including at least two columns of contacts for bringing the source interconnect and the snubber electrodes into contact with one another.

4. The semiconductor structure of claim 2 wherein each gate trench includes a shield electrode under the gate electrode.

5. The semiconductor structure of claim 2 wherein the snubber trenches extend deeper than the gate trenches.

6. The semiconductor structure of claim 2 wherein each snubber electrode is recessed in the corresponding snubber trench, and a dielectric layer insulates portions of each snubber electrode from the source interconnect layer.

7. The semiconductor structure of claim 2 wherein the snubber trenches and the gate trenches extend to the same depth, a dielectric layer extending along the bottom of each gate trench is thicker than a dielectric layer extending along the bottom of each snubber trench.

8. The semiconductor structure of claim 2 wherein the snubber trenches and gate trenches extend along parallel rows, the rows of snubber trenches being dispersed among the rows of gate trenches.

9. The semiconductor structure of claim 1 wherein the power transistor is formed in an entirely separate part of the die from the RC snubber.

10. The semiconductor structure of claim 1 wherein the power transistor is formed in an active region of the die, and the RC snubber is formed in a region extending under a gate pad that is electrically connected to the gate electrodes.

11. The semiconductor structure of claim 1 wherein the gate electrodes and the snubber electrodes laterally extend over but are insulated from a top surface of the silicon region.

12. The semiconductor structure of claim 1 wherein the snubber resistance is in the range of 0.5 to 2.0 Ohms.

13. The semiconductor structure of claim 1 wherein the snubber resistor has a value proportional to √

{square root over (L/C)}, where C represents the output capacitance of the power transistor when turned off, and L includes the parasitic inductance of a package in which the semiconductor structure is housed.

14. The semiconductor structure of claim 1 wherein the snubber capacitor has a value greater than the output capacitance of the power transistor when turned off.

15. A semiconductor die comprising:

a power transistor and an RC snubber monolithically integrated in the die, wherein;

the power transistor comprises gate electrodes arranged along rows, a drain interconnect contacting a drain region, and a source interconnect contacting source regions, and

the RC snubber comprises snubber electrodes arrange along rows parallel to the rows of gate electrodes, the snubber electrodes being insulated from the drain region by a snubber dielectric such that the snubber electrodes and the drain region form a snubber capacitor having a predetermined capacitance value,

the structure further comprising at least two columns of contacts for bringing the source interconnect and the snubber electrodes into contact with one another so as to form a snubber resistor having a predetermined resistor value, wherein the snubber capacitor and the snubber resistor function to substantially dampen output ringing when the power transistor switches states.

16. The semiconductor die of claim 15 wherein the snubber resistance is in the range of 0.5 to 2.0 Ohms.

17. The semiconductor die of claim 15 wherein the snubber resistor has a value proportional to √

{square root over (L/C)}, where C represents the output capacitance of the power transistor when turned off, and L includes the parasitic inductance of a package in which the semiconductor structure is housed.

18. The semiconductor die of claim 15 wherein the snubber capacitor has a value greater than the output capacitance of the power transistor when turned off.

19. A multi-chip module comprising:

a high-side switch including a high-side power transistor and a high-side RC snubber monolithically integrated in a first die, wherein the high-side power transistor includes a high-side drain interconnect, a high-side source interconnect, and a high-side gate interconnect, and the high-side RC snubber includes a high-side snubber capacitor and a high-side snubber resistor serially coupled between the high-side drain interconnect and the high-side source interconnect so as to substantially dampen output ringing when the high-side switch changes states; and

a low-side switch including a low-side power transistor and a low-side RC snubber monolithically integrated in a second die, the high-side and low-side switches being serially coupled, wherein the low-side power transistor includes a low-side drain interconnect, a low-side source interconnect, and a low-side gate interconnect, and the low-side RC snubber includes a low-side snubber capacitor and a low-side snubber resistor serially coupled between the low-side drain interconnect and the low-side source interconnect so as to substantially dampen output ringing when the low side power transistor switches states.

20. The multi-chip module of claim 19 wherein:

(a) the high-side power transistor further comprises;

body regions extending in a drain region, the high-side drain interconnect contacting the drain region;

gate electrodes insulated from the body region by a gate dielectric, the high-side gate interconnect contacting the gate electrodes;

source regions extending in the body regions, the source and the body regions being of opposite conductivity type, the high-side source interconnect contacting the source regions; and

(b) the high-side RC snubber further comprises;

snubber electrodes insulated from the drain region by a snubber dielectric such that the snubber electrodes and the drain region form the high-side snubber capacitor, the snubber electrodes being connected to the high-side source interconnect in a manner so as to form the high-side snubber resistor.

21. The multi-chip module of claim 19 wherein:

(a) the low-side power transistor further comprises;

body regions extending in a drain region, the low-side drain interconnect contacting the drain region;

gate electrodes insulated from the body region by a gate dielectric, the low-side gate interconnect contacting the gate electrodes;

source regions extending in the body regions, the source and the body regions being of opposite conductivity type, the low-side source interconnect contacting the source regions; and

(b) the low-side RC snubber further comprises;

snubber electrodes insulated from the drain region by a snubber dielectric such that the snubber electrodes and the drain region form the low-side snubber capacitor, the snubber electrodes being connected to the low-side source interconnect in a manner so as to form the low-side snubber resistor.