CHIP CARRIER BEARING LARGE SILICON FOR HIGH PERFORMANCE COMPUTING AND RELATED METHOD

• US 20100164030A1
• Filed: 12/31/2008
• Published: 07/01/2010
• Est. Priority Date: 12/31/2008
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Blackshear, Edmund D., Feger, Claudius, Oggioni, Stefano S.
• Application Number:
  US12/347,490
• Publication Number:
  US 20100164030A1
• Time in Patent Office: Days
• US Class Current: 257/432
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

Embodiments of the present invention provide a system and method for manufacturing integrated circuit (IC) chip packages. In one embodiment, the integrated circuit (IC) chip package can include an IC chip and a substrate coupled to the IC chip. The substrate can include a glass fiber re-enforced epoxy core, a plurality copper circuitry containing particle re-enforced epoxy layers symmetrically-oriented to each surface of the glass fiber re-enforced epoxy core, and an outermost amorphous glass layer on each surface of the plurality of layers. The IC chip can be coupled to copper circuitry bonded to one of the outermost amorphous glass layers.

Claims

1. An integrated circuit (IC) chip package comprising:

an IC chip; and

a substrate coupled to the IC chip, the substrate comprising;

a glass fiber re-enforced epoxy core, a plurality copper circuitry containing particle re-enforced epoxy layers symmetrically-oriented to each surface of the glass fiber re-enforced epoxy core, and an outermost amorphous glass layer on each surface of the plurality of layers,

wherein the IC chip is coupled to copper circuitry bonded to one of the outermost amorphous glass layers.

2. The chip package of claim 1, wherein the glass layer is one of chemical resistant glass (C-Glass), high-alkali glass (A-Glass), electrical grade glass (E-Glass), high-strength glass (S-Glass) and dielectric constant glass (D-Glass).

3. The chip package of claim 1, wherein the glass layer is optical glass.

4. The chip package of claim 1, further comprising an optical device.

5. The chip package of claim 4, wherein the optical device is a vertical cavity surface emitting laser (VCSEL) mounted on a top surface of the optical glass.

6. The chip package of claim 4, wherein the optical device is photodetector mounted on a top surface of the optical glass.

7. The chip package of claim 1, wherein a coefficient of thermal expansion (CTE) of the outermost amorphous glass layer is tuned to match the CTE of the IC chip.

8. The chip package of claim 1, further comprising an opening in the outermost amorphous glass layer, the opening for exposing an underneath circuit of the substrate.

9. The chip package of claim 1, wherein a coefficient of thermal expansion (CTE) of the outermost amorphous glass layer is tuned to approximately 8 to 18 parts per million per degree Celsius (ppm/°

C.).

10. The chip package of claim 9, further comprising an adhesive layer between the outermost amorphous glass layer and the plurality of layers.

11. A method for manufacturing integrated circuit (IC) chip packages, the method comprising:

forming a glass fiber re-enforced epoxy core;

forming a plurality copper circuitry containing, a plurality of particle re-enforced epoxy layers symmetrically-oriented to each surface of the glass fiber re-enforced epoxy core;

forming an outermost amorphous glass layer on each surface of the plurality of layers; and

,

mounting an IC chip to copper circuitry bonded to one of the outermost amorphous glass layers.

12. The method of claim 11, wherein forming an outermost amorphous glass layer includes selecting a glass from the group of consisting of chemical resistant glass (C-Glass), high-alkali glass (A-Glass), electrical grade glass (E-Glass), high-strength glass (S-Glass) and dielectric constant glass (D-Glass).

13. The method of claim 11, wherein forming an outermost amorphous glass layer includes selecting an optical glass.

14. The method of claim 13, further comprising mounting an optical device on a top surface of the optical glass.

15. The method of claim 14, wherein the mounting an optical device on a top surface of the optical glass includes mounting a vertical cavity surface emitting laser (VCSEL) on the top surface of the optical glass.

16. The method of claim 11, wherein forming an outermost amorphous glass layer includes laminating the outermost layer to the plurality of layers using pressure and thermal curing.

17. The method of claim 11, wherein forming an outermost amorphous glass layer includes pre-curing the outermost layer and bonding the outermost layer to the plurality of layers using pressure, heat and an adhesive layer.

18. The method of claim 11, wherein forming an outermost amorphous glass layer includes pre-curing the outermost amorphous glass layer and perforating the outermost amorphous glass layer with a desired connection pattern.

19. The method of claim 14, further comprising ablating an opening in the outermost amorphous glass layer.

20. The method of claim 19, further comprising filling the opening with a conductive paste prior to lamination.