SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

• US 20100164077A1
• Filed: 12/26/2009
• Published: 07/01/2010
• Est. Priority Date: 12/26/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Bando, Koji, Akiyama, Tatsuhiko, Misumi, Kazuyuki, Yamazaki, Akira, Izumi, Naoki
• Granted Patent: US 8,258,604 B2
• Time in Patent Office: Days
• US Class Current: 257/659
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/33 of a plurality of layer connectors
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01026 : Iron [Fe]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01064 : Gadolinium [Gd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type

Abstract

To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device.

A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.

Claims

1. A semiconductor device, comprising:

(a) a die pad;

(b) a plurality of leads disposed around the die pad;

(c) a semiconductor chip having a principal surface and a rear surface opposite to the principal surface, and including a plurality of magnetic memory elements and a plurality of bonding pads on the principal surface side, the semiconductor chip being disposed over the die pad;

(d) a first magnetic shield material disposed between the die pad and the rear surface of the semiconductor chip;

(e) a second magnetic shield material disposed over the principal surface of the semiconductor chip, and disposed so as to cover a region where the magnetic memory elements are formed;

(f) a plurality of bonding wires for electrically coupling the bonding pads to the leads, respectively; and

(g) a resin body sealing apart of the respective leads, the bonding wires, the die pad, the semiconductor chip, the first magnetic shield material, and the second magnetic shield material,

wherein an area of the second magnetic shield material is formed smaller than an area of the principal surface of the semiconductor chip, and

wherein a thickness of the second magnetic shield material is formed thicker than a thickness of the first magnetic shield material.

2. The semiconductor device according to claim 1,

wherein a plurality of dimples is formed in a surface of the second magnetic shield material.

3. The semiconductor device according to claim 1,

wherein an area of the die pad is formed smaller than an area of the first magnetic shield material, and wherein a plurality of dimples is formed in a surface of the first magnetic shield material exposed from the die pad.

4. The semiconductor device according to claim 2,

wherein the dimples formed in the surface of the second magnetic shield material are formed by etching.

5. The semiconductor device according to claim 3,

wherein the dimples formed in the surface of the first magnetic shield material are formed by etching.

6. The semiconductor device according to claim 1,

wherein the first magnetic shield material and the second magnetic shield material are formed from an alloy of nickel and iron.

7. The semiconductor device according to claim 1,

wherein the area of the first magnetic shield material is formed larger than the area of the principal surface of the semiconductor chip.

8. The semiconductor device according to claim 1,

wherein the area of the first magnetic shield material is formed to be the same as the area of the principal surface of the semiconductor chip.

9. The semiconductor device according to claim 1,

wherein the bonding pads are disposed around the principal surface of the semiconductor chip, and

wherein the second magnetic shield material is disposed inside the bonding pads.

10. A semiconductor device, comprising:

(a) a die pad;

(b) a plurality of leads disposed around the die pad and including a plurality of signal leads and a plurality of fixed potential leads;

(c) a semiconductor chip having a principal surface and a rear surface opposite to the principal surface, and including on the principal surface side a microprocessor unit that executes data processing according to a program, a memory unit that includes a plurality of magnetic memory elements, a plurality of signal bonding pads, and a plurality of fixed potential bonding pads, the semiconductor chip being disposed over the die pad;

(d) a plurality of signal bonding wires electrically coupling the signal bonding pads to the signal leads, respectively;

(e) a first fixed potential bonding wire electrically coupling a first group of the fixed potential bonding pads to a first group of the fixed potential leads, respectively;

(f) a first magnetic shield material disposed between the die pad and the rear surface of the semiconductor chip;

(g) a second magnetic shield material disposed over the principal surface of the semiconductor chip, and disposed so as to cover at least a region where the memory unit is formed;

(h) a plurality of second fixed potential bonding wires electrically coupling a second group of the fixed potential bonding pads to the first magnetic shield material, respectively; and

(i) a resin body sealing the signal bonding wires, the first fixed potential bonding wires, the second fixed potential bonding wires, a part of the respective leads, the die pad, the semiconductor chip, the first magnetic shield material, and the second magnetic shield material,

wherein an area of the die pad is formed smaller than an area of the first magnetic shield material;

wherein an area of the first magnetic shield material is formed larger than an area of the principal surface of the semiconductor chip; and

wherein each of the second group of the fixed potential bonding pads is coupled to the first magnetic shield material of a region exposed from the semiconductor chip in a planar view.

11. The semiconductor device according to claim 10,

wherein an area of the second magnetic shield material is formed smaller than the area of the first magnetic shield material, and

wherein a thickness of the second magnetic shield material is formed thicker than a thickness of the first magnetic shield material.

12. A semiconductor device, comprising:

(a) a die pad;

(b) a plurality of leads disposed around the die pad;

(c) a semiconductor chip having a principal surface and a rear surface opposite to the principal surface and including a plurality of magnetic memory elements and a plurality of bonding pads on the principal surface side, the semiconductor chip being disposed over the die pad;

(d) a first magnetic shield material disposed between the die pad and the rear surface of the semiconductor chip;

(e) a second magnetic shield material disposed over the principal surface of the semiconductor chip, and disposed so as to cover a region where the magnetic memory elements are formed;

(f) a plurality of bonding wires electrically coupling the bonding pads to the leads, respectively; and

(g) a resin body sealing apart of the respective leads, the bonding wires, the die pad, the semiconductor chip, the first magnetic shield material, and the second magnetic shield material,

wherein an area of the first magnetic shield material is formed larger than an area of the semiconductor chip, and

wherein the first magnetic shield material is bent so that an end thereof is positioned on a side face side of the semiconductor chip.

13. The semiconductor device according to claim 12,

wherein an area of the second magnetic shield material is formed smaller than an area of the first magnetic shield material, and

wherein a thickness of the second magnetic shield material is formed thicker than a thickness of the first magnetic shield material.

14. A semiconductor device, comprising:

(a) a die pad;

(b) a plurality of leads disposed around the die pad;

(c) a fixed potential lead disposed between the die pad and the leads in a planar view;

(d) a semiconductor chip having a principal surface and a rear surface opposite to the principal surface, and including a plurality of magnetic memory elements and a plurality of bonding pads on the principal surface side, the semiconductor chip being disposed over the die pad;

(e) a first magnetic shield material disposed between the die pad and the rear surface of the semiconductor chip;

(f) a second magnetic shield material disposed over the principal surface of the semiconductor chip, and disposed so as to cover a region where the magnetic memory elements are formed;

(g) a third magnetic shield material disposed in a surface of the fixed potential lead;

(h) a plurality of bonding wires electrically coupling the bonding pads to the leads and electrically coupling the bonding pads to the fixed potential lead, respectively; and

(i) a resin body sealing apart of the respective leads, the fixed potential lead, the bonding wires, the die pad, the semiconductor chip, the first magnetic shield material, the second magnetic shield material, and the third magnetic shield material,

wherein the fixed potential lead and the third magnetic shield material are disposed so that parts thereof are positioned on a side face side of the semiconductor chip in a cross sectional view.

15. The semiconductor device according to claim 14,

wherein an area of the second magnetic shield material is formed smaller than an area of the first magnetic shield material, and

wherein a thickness of the second magnetic shield material is formed thicker than a thickness of the first magnetic shield material.

16. A method of manufacturing a semiconductor device comprising the steps of:

(a) preparing a lead frame including a die pad and a plurality of leads disposed around the die pad;

(b) preparing a semiconductor wafer having a principal surface and a rear surface opposite to the principal surface, the semiconductor wafer including on the principal surface side a plurality of chip areas where a plurality of magnetic memory elements and a plurality of bonding pads are formed;

(c) sticking a first adhesive film material to the rear surface of the semiconductor wafer;

(d) after the step (c), sticking a first magnetic shield material to the rear surface of the semiconductor wafer via the first film material;

(e) after the step (d), sticking a second adhesive film material to a rear surface of the first magnetic shield material;

(f) after the step (e), dicing the semiconductor wafer and the first magnetic shield material stuck to the rear surface of the semiconductor wafer altogether and thereby forming a plurality of semiconductor chips to which the singulated first magnetic shield material is stuck;

(g) after the step (f), mounting the semiconductor chip, to which the first magnetic shield material is stuck, over the die pad so that the first magnetic shield material is sandwiched between the semiconductor chip and the die pad;

(h) disposing a second magnetic shield material over the principal surface of the semiconductor chip so as to cover a region where the magnetic memory elements are formed;

(i) electrically coupling the leads to the bonding pads with a plurality of bonding wires; and

(j) sealing a part of the leads, the bonding wires, the die pad, the semiconductor chip, the first magnetic shield material, and the second magnetic shield material with a resin body,

wherein an area of the second magnetic shield material is formed smaller than an area of the principal surface of the semiconductor chip, and

wherein a thickness of the second magnetic shield material is formed thicker than a thickness of the first magnetic shield material.

17. The method of manufacturing a semiconductor device according to claim 16,

wherein a plurality of dimples is formed in a surface of the second magnetic shield material by etching.

18. The method of manufacturing a semiconductor device according to claim 16,

wherein an area of the die pad is formed smaller than an area of the first magnetic shield material, and

wherein a plurality of dimples is formed in a surface of the first magnetic shield material exposed from the die pad, by etching.

19. The method of manufacturing a semiconductor device according to claim 16,

wherein the first magnetic shield material and the second magnetic shield material are formed from an alloy of nickel and iron.

20. A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing a die pad and a lead frame including a plurality of leads disposed around the die pad;

(b) preparing a semiconductor chip having a principal surface and a rear surface opposite to the principal surface, the semiconductor chip including on the principal surface side a plurality of magnetic memory elements and a plurality of bonding pads;

(c) mounting the semiconductor chip over the die pad;

(d) disposing a magnetic shield material over the principal surface of the semiconductor chip so as to cover a region where the magnetic memory elements are formed;

(e) electrically coupling the leads to the bonding pads with a plurality of bonding wires; and

(f) sealing a part of the respective leads, the bonding wires, the die pad, the semiconductor chip, and the magnetic shield material with a resin body;

wherein the magnetic shield material is a magnetic shield material formed by patterning a plate-like magnetic shield material by selective etching.

21. The method of manufacturing a semiconductor device according to claim 20,

wherein the etching is wet etching using an etchant.

22. A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing a die pad and a lead frame including a plurality of leads disposed around the die pad;

(b) preparing a semiconductor chip having a principal surface and a rear surface opposite to the principal surface, the semiconductor chip including on the principal surface side a plurality of magnetic memory elements and a plurality of bonding pads;

(c) mounting the semiconductor chip over the die pad;

(d) disposing a magnetic shield material over the principal surface of the semiconductor chip so as to cover a region where the magnetic memory elements are formed;

(e) electrically coupling the leads to the bonding pads with a plurality of bonding wires; and

(f) sealing a part of the respective leads, the bonding wires, the die pad, the semiconductor chip, and the magnetic shield material with a resin body,

wherein the step (b) includes the steps of;

(b1) preparing a semiconductor wafer where the magnetic memory elements are formed in each of a plurality of chip areas;

(b2) forming a polyimide resin film in a surface of the semiconductor wafer;

(b3) performing heat treatment at a predetermined temperature on the polyimide resin film; and

(b4) forming a plurality of the semiconductor chips having the polyimide resin film in a surface thereof by dicing the semiconductor wafer;

wherein the step (d) includes the step of bonding the magnetic shield material to a surface of the polyimide resin film formed in each of the semiconductor chips; and

wherein the predetermined temperature of the heat treatment in the step (b3) is 260°

C. or lower.