SEMICONDUCTOR PACKAGE APPARATUS AND MANUFACTURING METHOD THEREOF

• US 20100164090A1
• Filed: 12/27/2009
• Published: 07/01/2010
• Est. Priority Date: 12/30/2008
• Status: Abandoned Application

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Kim, Sang-Chul
• Application Number:
  US12/647,500
• Publication Number:
  US 20100164090A1
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0579 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/05799 Base material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81903 by means of a layer connector
• CPC Class Codes: H01L 2224/83851 being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0665 : Epoxy resin

Abstract

A semiconductor package apparatus includes a first semiconductor chip bonded onto a substrate of which metal wire turning upward; and a second semiconductor chip conductively bonded onto the first semiconductor chip in a vertical direction such that a metal wire of the second semiconductor chip and the metal wire of the first semiconductor chip have facing points. The semiconductor package apparatus includes a third semiconductor chip conductively bonded onto the first semiconductor chip in the vertical direction to be disposed horizontally with the second semiconductor chip such that a metal wire of the third semiconductor chip and the metal wire of the first semiconductor chip have facing points.

Claims

1. An apparatus comprising:

a substrate;

a first semiconductor chip bonded to the substrate, the first semiconductor chip having a first metal wire formed therein;

a second semiconductor chip conductively bonded to the first semiconductor chip, the second semiconductor chip having a second metal wire formed therein; and

a third semiconductor chip conductively bonded to the first semiconductor chip such that the third semiconductor chip is disposed laterally relative to the second semiconductor chip, the third semiconductor chip having a third metal wire formed therein,

wherein the second semiconductor chip is conductively bonded to the first semiconductor chip at an interface between the first metal wiring and the second metal wiring and the third semiconductor chip is conductively bonded to the first semiconductor chip at an interface between the first metal wiring and the third metal wiring.

2. The apparatus of claim 1, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film and a metal ball.

3. The apparatus of claim 1, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film, metal bumps, and an anisotropic conductive film.

4. The apparatus of claim 1, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film, a metal bump and photopolymerizable resin.

6. The apparatus of claim 1, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film and conductive particles.

7. The apparatus of claim 1, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film, conductive particles and photopolymerizable resin.

8. The apparatus of claim 1, wherein the apparatus comprises a semiconductor package.

9. A method comprising:

bonding a first semiconductor chip having a first metal wire to a substrate;

conductively bonding a second semiconductor chip having a second metal wire to the first semiconductor chip at an interface between the second metal wire and the first metal wire; and

conductively bonding a third semiconductor chip having a third metal wire to the first semiconductor chip at an interface between the third metal wire and the first metal wire such that the third semiconductor chip is disposed laterally relative to the second semiconductor chip.

10. The method of claim 9, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film and a metal ball.

11. The method of claim 9, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film, metal bumps and an anisotropic conductive film.

12. The method of claim 9, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film, metal bumps and photopolymerizable resin.

13. The method of claim 9, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film and conductive particles.

14. The method of claim 9, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film, conductive particles and photopolymerizable resin.

15. An apparatus comprising:

a substrate;

a first semiconductor chip having a plurality of first metal wires formed therein, the first semiconductor chip being bonded to the substrate at a first surface of the first semiconductor chip such that a second surface of the first semiconductor chip is exposed;

a second semiconductor chip having a plurality of second metal wires formed therein that are spatially aligned and corresponds to a first set of the first metal wires, the second semiconductor chip being conductively bonded to the first semiconductor chip at the exposed second surface of the first semiconductor chip and at an interface between the second metal wires and the first metal wires; and

a third semiconductor chip having a plurality of third metal wires formed therein that are spatially aligned and corresponds to a second set of the first metal wires, the third semiconductor chip being conductively bonded to the first semiconductor chip at the exposed second surface of the first semiconductor chip on the same plane as the second semiconductor chip and at an interface between the third metal wires and the first metal wires.

16. The apparatus of claim 15, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film and a metal ball.

17. The apparatus of claim 15, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film, metal bumps, and an anisotropic conductive film.

18. The apparatus of claim 15, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film, a metal bump and photopolymerizable resin.

19. The apparatus of claim 15, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film and conductive particles.

20. The apparatus of claim 15, wherein the second semiconductor chip and the third semiconductor chip are conductively bonded to the first semiconductor chip, respectively, using a conductive film, conductive particles and photopolymerizable resin.