FAST DIFFERENTIAL LEVEL SHIFTER AND BOOT STRAP DRIVER INCLUDING THE SAME

• US 20100164593A1
• Filed: 12/23/2009
• Published: 07/01/2010
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Hong, Seung-Hun, Ha, Chang-Woo
• Granted Patent: US 8,054,123 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A boot strap driver including a fast differential level shifter are disclosed. The fast differential level shifter may include a first differential amplifier differentially amplifying a pulse width modulation signal and an inverted pulse width modulation signal and outputting a first differential amplification voltage and a second differential amplification voltage based on the amplified result. The fast differential level shifter may also include a second differential amplifier differentially amplifying the first differential amplification voltage and the second differential amplification voltage, and shifting the differential amplification voltages to voltages having an output range between a first voltage and a second voltage based on the amplified result.

Claims

1. An apparatus comprising:

a first differential amplifier differentially amplifying a pulse width modulation signal and an inverted pulse width modulation signal and outputting a first differential amplification voltage and a second differential amplification voltage based on the amplified result; and

a second differential amplifier differentially amplifying the first differential amplification voltage and the second differential amplification voltage, and shifting the differential amplification voltages to voltages having an output range between a first voltage and a second voltage based on the amplified result.

2. The apparatus of claim 1, wherein the first differential amplifier includes:

a pair of first differential transistors to which the pulse width modulation signal and the inverted pulse width modulation signal are differentially input.

3. The apparatus of claim 2, wherein the first differential amplifier includes a load part connected between a first power source and output terminals of the pair of first differential transistors, clamping the output voltage of the first differential transistors.

4. The apparatus of claim 2, wherein the first differential amplifier includes a bias resistor connected between a tail of the pair of first differential transistors and a ground power source.

5. The apparatus of claim 4, wherein the first differential amplifier includes a first load transistor connected between a first output terminal of output terminals of the pair of differential transistors and a first boot strap power source, including a gate connected to a second output terminal of the output terminals of the pair of differential transistors.

6. The apparatus of claim 5, wherein the first differential amplifier includes a second load transistor connected between the first boot strap power source and the second output terminal, including a gate connected to the first output terminal.

7. The apparatus of claim 1, wherein the first differential amplifier includes:

a pair of first differential transistors to which the pulse width modulation signal and the inverted pulse width modulation signal are differentially input;

a bias resistor connected between a tail of the pair of first differential transistors and a ground power source;

a first inner pressure protective resistor connected between a first output terminal of the pair of first differential transistors and a first node;

a second inner pressure protective resistor connected between a second output terminal of the pair of first differential transistors and a second node;

a first load transistor connected between the first node and the first boot strap power source, including a gate connected to the second node; and

a second load transistor connected between the second node and the first boot strap power source, including a gate connected to the first node.

8. The apparatus of claim 7, wherein the first differential amplifier includes a first clamping diode connected between the first power source and the first node in a forward direction from the first boot strap power source to the first node.

9. The apparatus of claim 8, wherein the first differential amplifier includes a second clamping diode connected between the first power source and the second node in a forward direction from the first power source to the second node.

10. The apparatus of claim 7, wherein the second differential amplifier includes a pair of second differential transistors to which the first differential amplification voltage and the second differential amplification voltage are differentially input, having a tail connected to the first boot strap power source.

11. The apparatus of claim 10, wherein the second differential amplifier includes a third load transistor connected between a first output terminal of output terminals of the pair of second differential transistors and a second boot strap power source, including a gate connected to a second output terminal of the output terminals of the pair of second differential transistors.

12. The apparatus of claim 11, wherein the second differential amplifier includes a fourth load transistor connected between the second output terminal and the second boot strap power source, including a gate connected to the first output terminal.

13. The apparatus of claim 10, wherein one of the pair of second differential transistors includes a gate connected to the first node, and the other one of the pair of second differential transistors includes a gate connected to the second node.

14. The apparatus of claim 12, including a second inverter connected to any one of the first output terminal and the second output terminal and biased by the first boot strap power source and the second boot strap power source.

15. The apparatus of claim 7, wherein the pair of first differential transistors and the pair of second differential transistors are NMOS transistors, and the first load transistor and the second load transistor are PMOS transistors.

16. An apparatus comprising:

a pulse width modulation signal generator generating a pulse width modulation signal;

a level shifter shifting the pulse width modulation signal to a boot strap output voltage having a voltage range from a first boot strap voltage to a second boot strap voltage by differentially amplifying the pulse width modulation signal in two stages; and

an upper driver biased by the first and second boot strap voltages, driving the output of the level shifter and outputting a first driven signal,

wherein the level shifter differentially amplifies the pulse width modulation signal and an inverted pulse width modulation signal, outputs a first differential amplification voltage and a second differential amplification voltage based on the amplified result, differentially amplifies the first differential amplification voltage and the second differential amplification voltage, and outputs the boot strap output voltage based on the amplified result.

17. The apparatus of claim 16, wherein the level shifter includes a first differential amplifier differentially amplifying the pulse width modulation signal and the inverted pulse width modulation signal and outputting the first differential amplification voltage and the second differential amplification voltage based on the amplified result.

18. The apparatus of claim 17, wherein the level shifter includes a second differential amplifier differentially amplifying the first differential amplification voltage and the second differential amplification voltage and outputting the boot strap output voltage having an output range between a first voltage and a second voltage based on the amplified result.

19. The apparatus of claim 18, wherein the first differential amplifier includes a pair of first differential transistors to which the pulse width modulation signal and the inverted pulse width modulation signal are differentially input.

20. The apparatus of claim 19, wherein the first differential amplifier includes a load part connected between a first power source and output terminals of the pair of first differential transistors, clamping the output voltage of the first differential transistors.