SEMICONDUCTOR INTEGRATED CIRCUIT

• US 20100164605A1
• Filed: 12/31/2009
• Published: 07/01/2010
• Est. Priority Date: 12/31/2008
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Hyung-Dong, Kim, Hyun-Seok, LEE, Jun-Ho
• Application Number:
  US12/650,592
• Publication Number:
  US 20100164605A1
• Time in Patent Office: Days
• US Class Current: 327/530
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor integrated circuit is capable of minimizing/decreasing the increase in the inductance of a package due to a power supply network thereof. The semiconductor integrated circuit includes a first power mesh configured to supply a first power to a first internal circuit, a second power mesh configured to supply a second power to a second internal circuit, the first power and the second power being used for different purposes and being equal in DC level, and a connection unit configured to connect the first power mesh to the second power mesh.

Claims

1. A semiconductor integrated circuit, comprising:

a first power mesh configured to supply a first power to a first internal circuit;

a second power mesh configured to supply a second power to a second internal circuit, the first power and the second power being used for different purposes and being equal in DC level; and

a connection unit configured to connect the first power mesh to the second power mesh.

2. The semiconductor integrated circuit of claim 1, wherein the connection unit includes a metal interconnection configured to connect the first power mesh to the second power mesh.

3. A semiconductor integrated circuit, comprising:

a first power mesh configured to supply a first external power voltage to a first internal circuit; and

a second power mesh configured to supply a second external power supply voltage to a second internal circuit,

wherein the first external power supply voltage and the second external power supply voltage are used for different purposes and are equal in DC level, and the first power mesh and the second power mesh are electrically connected to each other.

4. The semiconductor integrated circuit of claim 3, wherein the first external power supply voltage includes a general-purpose power supply voltage, and the second external power supply voltage includes a power supply voltage dedicated to an output driver.

5. The semiconductor integrated circuit of claim 3, wherein the first external power supply voltage includes a general-purpose power supply voltage, and the second external power supply voltage includes a power supply voltage dedicated to a delay locked loop (DLL).

6. A semiconductor integrated circuit, comprising:

a first power mesh configured to supply a first ground voltage to a first internal circuit; and

a second power mesh configured to supply a second ground voltage to a second internal circuit,

wherein the first ground voltage and the second ground voltage are used for different purposes, and the first power mesh and the second power mesh are electrically connected to each other.

7. The semiconductor integrated circuit of claim 6, wherein the first ground voltage includes a general-purpose ground voltage and the second ground voltage includes a ground voltage dedicated to an output driver.

8. The semiconductor integrated circuit of claim 6, wherein the first ground voltage includes a general-purpose ground voltage and the second ground voltage includes a ground voltage dedicated to a delay locked loop (DLL).