Channel Scan Logic
First Claim
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1. Channel scan logic for controlling scanning functions of a sensor panel, comprising:
- a clock generator configured to generate a clock signal based on one of a plurality timing parameters inputted into the clock generator;
a stimulus signal divider operatively connected to the clock generator, the stimulus frequency divider configured to output a stimulus signal by dividing a the clock signal by a stimulus divide parameter;
a count divider operatively connected to the clock generator, the count divider configured to divide the clock signal by a count divide parameter to produce a count clock signal;
a counter operatively connected to the count divider, the counter configured to generate a plurality of incremented signals in response to the count clock signal;
a demodulation look up table operatively connected to the counter, the demodulation look up table outputting a demodulation value corresponding to each of the plurality of incremented signals;
a channel timing generator configured receive channel timing parameters and generate an analog channel control signal based on the channel timing parameters;
a sensor address generator configured to receive sensor address parameters and generate a sensor address control signal based on the sensor address parameters; and
delay logic operatively connected to the channel timing generator and the demodulation lookup table, the delay logic configured to generate delayed demodulation waveform signals and delayed analog to digital control signals.
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Abstract
A device that can autonomously scan a sensor panel is disclosed. Autonomous scanning can be performed by implementing channel scan logic. In one embodiment, channel scan logic carries out many of the functions that a processor would normally undertake, including generating timing sequences and obtaining result data; comparing scan result data against a threshold value (e.g., in an auto-scan mode); generating row count; selecting one or more scanning frequency bands; power management control; and performing an auto-scan routine in a low power mode.
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Citations
12 Claims
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1. Channel scan logic for controlling scanning functions of a sensor panel, comprising:
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a clock generator configured to generate a clock signal based on one of a plurality timing parameters inputted into the clock generator; a stimulus signal divider operatively connected to the clock generator, the stimulus frequency divider configured to output a stimulus signal by dividing a the clock signal by a stimulus divide parameter; a count divider operatively connected to the clock generator, the count divider configured to divide the clock signal by a count divide parameter to produce a count clock signal; a counter operatively connected to the count divider, the counter configured to generate a plurality of incremented signals in response to the count clock signal; a demodulation look up table operatively connected to the counter, the demodulation look up table outputting a demodulation value corresponding to each of the plurality of incremented signals; a channel timing generator configured receive channel timing parameters and generate an analog channel control signal based on the channel timing parameters; a sensor address generator configured to receive sensor address parameters and generate a sensor address control signal based on the sensor address parameters; and delay logic operatively connected to the channel timing generator and the demodulation lookup table, the delay logic configured to generate delayed demodulation waveform signals and delayed analog to digital control signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification