CHIP PACKAGES WITH POWER MANAGEMENT INTEGRATED CIRCUITS AND RELATED TECHNIQUES

• US 20100165585A1
• Filed: 12/22/2009
• Published: 07/01/2010
• Est. Priority Date: 12/26/2008
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Application Number:
  US12/645,361
• Publication Number:
  US 20100165585A1
• Time in Patent Office: Days
• US Class Current: 361/748
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/0615 : Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16245 : the item being metallic
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/642 : Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Chip packages having power management integrated circuits are described. Power management integrated circuits can be combined with on-chip passive devices, and can provide voltage regulation, voltage conversion, dynamic voltage scaling, and battery management or charging. The on-chip passive devices can include inductors, capacitors, or resistors. Power management using a built-in voltage regulator or converter can provide for immediate adjustment of the voltage range to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices. Related fabrication techniques are described.

Claims

1. A chip package comprising:

a substrate;

a first chip over the substrate;

a second chip over the substrate; and

a voltage regulator device over the substrate, wherein the voltage regulator device is configured and arranged to accommodate different voltage needs of the first chip and second chip.

2. The chip package of claim 1, wherein the voltage regulator device comprises a semiconductor chip, wherein the semiconductor chip includes:

a silicon substrate;

multiple active devices in or over the silicon substrate, wherein the active devices comprise a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices;

a first dielectric layer over the silicon substrate;

a metallization structure over the first dielectric layer, wherein the metallization structure is connected to the active devices, and wherein the metallization structure comprises a first metal layer and a second metal layer over the first metal layer;

a second dielectric layer between the first and second metal layers;

a passivation layer over the metallization structure and over the first and second dielectric layers, an opening in the passivation layer exposing a pad and a contact pad of the metallization structure; and

an inductor component and a capacitor component connected to the pads through a first solder layer, wherein the inductor component, the capacitor component, the switch controller and the voltage feedback device form the voltage regulator.

3. The chip package of claim 2, wherein the passivation layer comprises a silicon nitride layer having a thickness of more than 0.3 micrometers.

4. The chip package of claim 2, further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is over the under bump metal structure.

5. The chip package of claim 4, wherein the under bump metal structure comprises a nickel layer.

6. The chip package of claim 4, wherein the under bump metal structure comprises a copper layer.

7. The chip package of claim 1, wherein the second chip is over the first chip.

8. The chip package of claim 1, wherein the substrate comprises a Ball Grid Array (BGA) substrate.

9. A chip package comprising:

a substrate;

a first chip over the substrate;

a second chip over the substrate; and

a voltage converter device over the substrate, wherein the voltage regulator device is configured and arranged to accommodate different voltage needs of the first chip and second chip.

10. The chip package of claim 9, wherein the voltage converter device comprises a semiconductor chip, wherein the semiconductor chip includes:

a silicon substrate;

multiple active devices in or over the silicon substrate, wherein the active devices comprise a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices;

a first dielectric layer over the silicon substrate;

a metallization structure over the first dielectric layer, wherein the metallization structure is connected to the active devices, and wherein the metallization structure comprises a first metal layer and a second metal layer over the first metal layer;

a second dielectric layer between the first and second metal layers;

a passivation layer over the metallization structure and over the first and second dielectric layers, an opening in the passivation layer exposing a pad and a contact pad of the metallization structure; and

an inductor component and a capacitor component connected to the pads through a first solder layer, wherein the inductor component, the capacitor component, the switch controller and the voltage feedback device form an on-chip voltage converter.

11. The chip package of claim 10, wherein the passivation layer comprises a silicon nitride layer having a thickness of more than 0.3 micrometers.

12. The chip package of claim 10, further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is over the under bump metal structure.

13. The chip package of claim 12, wherein the under bump metal structure comprises a nickel layer.

14. The chip package of claim 12, wherein the under bump metal structure comprises a copper layer.

15. The chip package of claim 9, wherein the second chip is over the first chip.

16. The chip package of claim 9, wherein the substrate comprises a ball grid array (BGA) substrate.

17. A chip package comprising:

a substrate;

a first chip over the substrate;

a second chip over the substrate; and

a power management device over the substrate, wherein the power management device is configured and arranged to accommodate different voltage needs of the first chip and the second chip.

18. The chip package of claim 17, wherein the power management device comprises a semiconductor chip, wherein the semiconductor chip includes:

a silicon substrate;

multiple active devices in or over the silicon substrate, wherein the active devices comprise a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices;

a first dielectric layer over the silicon substrate;

a metallization structure over the first dielectric layer, wherein the metallization structure is connected to the active devices, and wherein the metallization structure comprises a first metal layer and a second metal layer over the first metal layer;

a second dielectric layer between the first and second metal layers;

a passivation layer over the metallization structure and over the first and second dielectric layers, an opening in the passivation layer exposing a pad and a contact pad of the metallization structure; and

an inductor component and a capacitor component connected to the pads through a first solder layer.

19. The chip package of claim 18, wherein the passivation layer comprises a silicon nitride layer having a thickness of more than 0.3 micrometers.

20. The chip package of claim 18, further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is over the under bump metal structure.

21. The chip package of claim 20, wherein the under bump metal structure comprises a nickel layer.

22. The chip package of claim 20, wherein the under bump metal structure comprises a copper layer.

23. The chip package of claim 17, wherein the second chip is over the first chip.

24. The chip package of claim 17, wherein the substrate comprises a Ball Grid Array (BGA) substrate.