NON-VOLATILE ONE-TIME - PROGRAMMABLE AND MULTIPLE-TIME PROGRAMMABLE MEMORY CONFIGURATION CIRCUIT

• US 20100165698A1
• Filed: 12/30/2009
• Published: 07/01/2010
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Liu, David K.Y.
• Granted Patent: US 8,203,861 B2
• Time in Patent Office: Days
• US Class Current: 365/94
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: G11C 2216/26 Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H03K 19/0002 Multistate logic H03K19/02 takes precedence
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications.

Claims

1. In a field programmable gate array (FPGA) or programmable logic device (PLD) coupled to a programmable non-volatile configuration storage bit circuit the improvement comprising:

a first floating gate associated with a first non-volatile device;

a second floating gate associated with a second non-volatile device;

a first drain region associated with said first non-volatile memory device; and

a second drain region associated with said second non-volatile memory device; and

wherein the first drain region and the second drain region overlap respective sufficient portions of said first floating gate and said second floating gate respectively such that a programming voltage applied to said drains can be imparted to said floating gates through capacitive coupling;

an output coupled to said first non-volatile device and said second non-volatile device;

wherein a value of said output of said programmable non-volatile circuit is based on a programmed state of said first non-volatile device and said second non-volatile memory device and can be used to configure a function to be performed by the FPGA or PLD.

2. The programmable non-volatile circuit of claim 1 wherein both first and second non-volatile devices are n-channel.

3. The programmable non-volatile circuit of claim 1 wherein at least one of said first floating gate and second floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory.

4. The programmable non-volatile circuit of claim 1 wherein said first non-volatile device is a pull-up device coupled to a first voltage source, and said second non-volatile device is a pull-down device coupled to a second voltage source which has less potential than said first voltage source.

5. The programmable non-volatile circuit of claim 1 wherein at least one of said first floating gate and second floating gate can be erased.

6. The programmable non-volatile circuit of claim 5 wherein at least one of said first floating gate and second floating gate can be re-programmed.

7. A one-time programmable (OTP) configuration circuit incorporated on a silicon substrate with one or more other additional logic and/or non-OTP configuration circuits, characterized in that:

a. said OTP configuration circuit has an OTP n-type channel pull-up memory device coupled to an OTP n-type channel pull-down memory device;

b. any and all regions and structures of said OTP n-type channel pull-up memory device and OTP n-type channel pull-down memory device are derived solely from corresponding regions and structures used as components of other logic devices within a programmable logic circuit or field programmable gate array circuit.

8. The OTP configuration circuit of claim 7, wherein a common node between said OTP n-type channel pull-up memory device and OTP n-type channel pull-down memory device provides an output voltage value to a separate CMOS logic gate.

9. The OTP configuration circuit of claim 8 wherein said output voltage value can be varied between a first high reference potential and a second low reference potential.

10. The OTP configuration circuit of claim 7, wherein a channel implant in said OTP n-type channel pull-up memory device is provided to allow said output value to reach a reference potential Vcc used by the OTP configuration circuit.

11. A configuration circuit coupled to a field programmable gate array (FPGA) or programmable logic device (PLD) and comprising:

a. a non-volatile pull-up device adapted to cause a first logical value to be presented at an output of the configuration circuit;

b. a non-volatile pull-down device coupled to said non-volatile pull-up device and adapted to cause a second logical to be presented at said output;

wherein each of said non-volatile pull-up device and said non-volatile pull-down device has a drain region capacitively coupled to a floating gate, such that a programming charge applied to said drain region can be imparted to said floating gate;

further wherein a conductance of said a non-volatile pull-up device or said non-volatile pull-down device can be permanently set to a first state or a second state to control said output provided to the FPGA or PLD.

12. The OTP configuration circuit of claim 11, wherein a channel implant in said non-volatile pull-up device is provided to allow said output value to reach a full reference potential Vcc used by the configuration circuit.