NONVOLATILE SEMICONDUCTOR MEMORY CAPABLE OF TRIMMING AN INITIAL PROGRAM VOLTAGE FOR EACH WORD LINE

• US 20100165740A1
• Filed: 03/08/2010
• Published: 07/01/2010
• Est. Priority Date: 01/24/2006
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: NAGASHIMA, Hiroyuki, Fukuda, Yasuyuki
• Granted Patent: US 7,881,116 B2
• Time in Patent Office: Days
• US Class Current: 365/185.190
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

A nonvolatile semiconductor memory of the present invention includes a plurality of bit lines and word lines which are arranged to intersect each other; a memory cell array having a plurality of electrically-programmable memory cells arranged in a region in which the bit lines and the word lines intersect; a trimming circuit configured to obtain a parameter of an initial program voltage for each word line of the plurality of word lines; an initial Vpgm parameter register configured to receive the parameter of the initial program voltage from the trimming circuit and to store the parameter; and a control circuit configured to perform programming of data to the memory cell array based on the parameter of the initial program voltage stored in the initial Vpgm parameter register, the trimming circuit being arranged in a part of the control circuit.

Claims

1. A nonvolatile semiconductor memory comprising:

a plurality of bit lines and word lines arranged to intersect each other, said plurality of word lines being divided into a plurality of word line groups, said plurality of word line groups including said plurality of word lines;

a memory cell array having a plurality of memory cell groups comprised of a plurality of electrically-programmable memory cells arranged in a region in which said bit lines and said word lines intersect;

a trimming circuit which obtains a parameter of an initial program voltage for each of said plurality of word line groups;

an initial Vpgm parameter register which receives said parameter of said initial program voltage for each of said plurality of word line groups from said trimming circuit and stores said parameter; and

a control circuit which programs data to each of said plurality of memory cell groups based on said parameter of said initial program voltage for each of said plurality of word line groups stored in said initial Vpgm parameter register, said trimming circuit being arranged in a part of said control circuit.

2. The nonvolatile semiconductor memory in claim 1, wherein said trimming circuit comprises:

a Vpgm increment command register which outputs an increment command which gradually increases said initial program voltage for each of said plurality of word line groups based on said parameter of said plurality of word line groups stored in said initial Vpgm parameter register; and

a trimming shift register which sets a trimming parameter for trimming said initial program voltage for each of said plurality of word line groups according to said increment command output from said Vpgm increment command register.

3. The nonvolatile semiconductor memory in claim 2, wherein said trimming circuit comprises:

an increment count accumulation register which accumulates an increment count of said initial program voltage for each of said plurality of word line groups according to said increment command output from said Vpgm increment command register;

an accumulate value equation shift register which averages said increment count accumulated by said increment count accumulation register for each of said plurality of word line groups; and

an adder which adds a value averaged by said accumulate value equation shift register to said initial program voltage and wherein said trimming shift register sets said trimming parameter for trimming said initial program voltage for each of said plurality of word line groups according to said increment command output from said Vpgm increment command register.

4. The nonvolatile semiconductor memory in claim 3, wherein said trimming circuit comprises:

a register data transfer command register which transfers said trimming parameter set by said trimming shift register to said initial Vpgm parameter register for each of said plurality of word line groups, and said initial Vpgm parameter register stores said trimming parameter for each of said plurality of word lines groups.

5. The nonvolatile semiconductor memory in claim 4, wherein:

said initial Vpgm parameter register is provided for each of said plurality of word line groups.

6. The nonvolatile semiconductor memory in claim 5, wherein:

said initial Vpgm parameter register of each of said plurality of word line groups is set with an address corresponding to each of said plurality of word line groups connected to said initial Vpgm parameter register.

said register data transfer command register transfers said trimming parameter of each of said plurality of word line groups to said initial Vpgm parameter register of each of said plurality of word line groups corresponding to said address; and

said initial Vpgm parameter register stores said trimming parameter of each of said plurality of word line groups.

7. The nonvolatile semiconductor memory in claim 2, wherein:

said initial Vpgm parameter register stores a voltage shift value as said trimming parameter, in which said initial program voltage is increased and decreased by said voltage shift value; and

said trimming shift register sets said trimming parameter for trimming said initial program voltage for each of said plurality of word line groups based on said voltage shift value stored in said initial Vpgm parameter register.

8. The nonvolatile semiconductor memory in claim 7, wherein:

said initial program voltage is an average value of said initial program voltage corresponding to each of said plurality of word line groups;

said Vpgm increment command register outputs a trimming command for trimming said initial program voltage for each of said plurality of word line groups based on said voltage shift value stored in said initial Vpgm parameter register; and

said trimming shift register sets said trimming parameter for trimming said initial voltage for each of said plurality of word line groups according to said trimming command output from said Vpgm command register.

9. The nonvolatile semiconductor memory in claim 7, wherein:

said initial Vpgm parameter register stores a minimum value of said voltage shift value; and

when said trimming shift register trims said initial programming voltage for each of said plurality of word line groups, said trimming shift register sets said trimming parameter by adding said minimum value to said initial program voltage based on said minimum value of said voltage shift value stored in said initial Vpgm parameter register.

10. The nonvolatile semiconductor memory in claim 7, wherein said trimming circuit comprises:

an increment count accumulation register which accumulates a trimming count of a voltage shift value according to said trimming command which is output from said Vpgm increment command register;

an accumulate value equation shift register which averages said trimming count accumulated by said increment count accumulation register;

an adder which adds a value averaged by said accumulate value equation shift register to said voltage shift value; and

wherein said trimming register sets said trimming parameter for trimming said initial programming voltage for each of said plurality of word line groups based on said voltage shift value and an addition value added by said adder.

11. The nonvolatile semiconductor memory in claim 7, wherein said trimming circuit comprises:

a register data transfer command register which transfers said trimming parameter set by said trimming shift register to said initial Vpgm parameter register and stores said trimming parameter for each of said plurality of word line groups in said initial Vpgm parameter register.

12. The nonvolatile semiconductor memory in claim 11, wherein:

said initial parameter register is provided for each of said plurality of word line groups.

13. The nonvolatile semiconductor memory as claimed in claim 12, wherein:

said initial Vpgm parameter register is set with an address for each of said plurality of word line groups connected to said initial Vpgm parameter register;

said register data transfer command register transfers said trimming parameter to said initial Vpgm parameter register corresponding to said address; and

said initial Vpgm parameter register stores said trimming parameter.

14. The nonvolatile semiconductor memory in claim 1, wherein:

said plurality of word lines are divided into groups corresponding to an arrangement region of said plurality of electrically-programmable memory cells within said memory cell array.