Non-Volatile Memory And Method With Continuous Scanning Time-Domain Sensing

• US 20100165743A1
• Filed: 12/31/2008
• Published: 07/01/2010
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Cernea, Raul-Adrian
• Granted Patent: US 7,944,754 B2
• Time in Patent Office: Days
• US Class Current: 365/185.210
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

A page of non-volatile multi-level memory cells on a word line is sensed in parallel by sense amps via bit lines. A predetermined input sensing voltage as an increasing function of time applied to the word line allows scanning of the entire range of thresholds of the memory cell in one sweep. Sensing of the thresholds of individual cells is then reduced to a time-domain sensing by noting the times the individual cells become conducting. Each conducting time, adjusted for delays in the word line and the bit line, can be used to derive the sensing voltage level that developed at the word line local to the cell when the cell became conducting. The locally developed sensing voltage level yields the threshold of the cell. This time-domain sensing is relative insensitive to the number of levels of a multi-level memory and therefore resolve many levels rapidly in one sweep.

Claims

1. A method of sensing a group of nonvolatile storage elements in parallel, comprising:

providing a word line for accessing the group of storage elements positioned from an input end of the word line at positions x1, x2, . . . xi, . . . xn;

providing an input scanning sense voltage V_INWL(t) applied to the input end of the word line;

predetermining a word line response function V_WL(xi, t) having a voltage amplitude as a function of xi and time, the response function being the word line electrical response to the input scanning sense voltage V_INWL(t) applied to the input end of the word line;

with application of the sensing voltage V_INWL(t) to the word line, determining a time marker ti at each storage element of the group indicating a time when the storage element begins to conduct current; and

determining the threshold voltage VTi of each storage element by evaluating the word line response function at the position of the storage element and at a time indicated by the time marker ti associated with the storage element.

2. The method as in claim 1, wherein:

the predetermined input scanning sensing voltage increases monotonically with time.

3. The method as in claim 1, wherein:

the predetermined input scanning sensing voltage has a predetermined constant ramp rate.

4. The method as in claim 1, wherein the nonvolatile storage elements are part of flash memory cells.

5. The method as in claim 1, wherein the nonvolatile storage elements are organized in an array thereof in a NAND configuration.

6. The method as in claim 1, wherein:

said determining the time marker for a storage element includes detecting the conduction current by a sense amplifier coupled to the storage element via a bit line, the time indicated by the time marker being the detection time at the sense amplifier offset by a predetermined bit line delayed period.

7. The method as in claim 6, wherein:

said determining the threshold voltage VTi of each storage element by evaluating the word line response function at the position of the storage element and at a time indicated by the time marker ti amounts to evaluating the input scanning sense voltage function at the detection time by the sense amplifier but shifted in time by a predetermined word line delay period and the predetermined bit line delay period.

8. The method as in claim 7, wherein:

the predetermined word line delay period is a predetermined function of the position of each storage element from the input end.

9. A method of sensing in parallel a group of nonvolatile storage elements among an array thereof, comprising:

providing a word line for accessing the group of storage elements positioned from an input end of the word line at positions x1, x2, . . . xi, . . . xn;

providing an input scanning sense voltage V_INWL(t) applied to the input end of the word line;

providing a sense amplifier coupled to each storage element via a bit line to determine a detected conduction time when the storage element starts to conduct in response to the input scanning sense voltage;

predetermining for each storage element a word line delay for the input scanning sense voltage to reach the storage element and a bit line delay for the conduction at the storage element to be detected by the sense amplifier; and

determining the threshold voltage VTi of each storage element by evaluating the input scanning sense voltage V_INWL(t) at the detected conduction time adjusted for the word line delay and the bit line delay.

10. The method as in claim 9, wherein:

the predetermined input scanning sensing voltage increases monotonically with time.

11. The method as in claim 9, wherein:

the predetermined input scanning sensing voltage has a predetermined constant ramp rate.

12. The method as in claim 9, wherein the nonvolatile storage elements are part of flash memory cells.

13. A nonvolatile memory, comprising:

an array of memory cells;

a word line for accessing the group of memory cells in parallel;

an input scanning sense voltage V_INWL(t) supplied to said word line from the input end;

a sense amplifier coupled to each storage element via a bit line to determine a detected conduction time when the storage element starts to conduct in response to the input scanning sense voltage;

each storage element having a predetermined a word line delay for the input scanning sense voltage to reach the storage element and a bit line delay for the conduction at the storage element to be detected by the sense amplifier; and

a controller for determining the threshold voltage VTi of each storage element by evaluating the input scanning sense voltage V_INWL(t) at the detected conduction time adjusted for the word line delay and the bit line delay associated with said each storage element.

14. The nonvolatile memory as in claim 13, wherein:

the predetermined input scanning sensing voltage increases monotonically with time.

15. The nonvolatile memory as in claim 13, wherein:

the predetermined input scanning sensing voltage has a predetermined constant ramp rate.

16. The nonvolatile memory as in claim 13, wherein the nonvolatile storage elements are part of flash memory cells.

17. The nonvolatile memory as in claim 13, wherein the nonvolatile storage elements are organized in an array thereof in a NAND configuration.