METHOD FOR FORMING FINE PATTERNS IN A SEMICONDUCTOR DEVICE

• US 20100167211A1
• Filed: 06/26/2009
• Published: 07/01/2010
• Est. Priority Date: 12/30/2008
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Dong Seok, LEE, Jin Yul
• Application Number:
  US12/492,720
• Publication Number:
  US 20100167211A1
• Time in Patent Office: Days
• US Class Current: 430/313
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/32139 using masks

Abstract

A method for forming fine patterns in a semiconductor device includes forming a first mask layer over an etch target layer, forming a first pattern over the first mask layer, reducing a size of the first pattern, forming a first spacer on a side face of the first pattern, removing the first pattern and patterning the first mask layer using the first spacer as a mask and removing the first spacer. The method also includes oxidating a surface of the patterned first mask layer, forming the first mask layer with reduced size by removing the oxidated portion over the surface of the first mask layer, forming a second spacer on a side wall of the first mask layer and removing the first mask layer, and patterning the etch target layer using the second spacer as a mask.

Claims

1. A method for forming fine patterns in a semiconductor device, the method comprising:

forming a hard mask layer over an etch target layer;

forming a plurality of first patterns with a predetermined width and space over the hard mask layer;

reducing size of the first patterns;

forming first spacers on side walls of the first patterns and removing the first patterns;

patterning the hard mask layer using the first spacers as mask to form a hard mask patterns and removing the first spacers;

oxidating surfaces of the hard mask patterns;

removing the oxidated portion over the surfaces of the hard mask patterns;

forming second spacers on side walls of the hard mask patterns and removing the hard mask patterns; and

,

patterning the etch target layer using the second spacers as mask.

2. The method of claim 1, wherein the etch target layer comprises a single layer or a multi-layer.

3. The method of claim 1, wherein the first pattern comprises a material having an etch selectivity to the hard mask layer.

4. The method of claim 3, wherein the hard mask layer comprises a polysilicon layer, a metal layer, or a silicide, and

the first pattern comprises a material selected from the group consisting of oxide, nitride, amorphous carbon, and silicon oxynitride (SiON).

5. The method of claim 1, wherein the reducing the size of the first pattern comprises isotropic etching the first pattern.

6. The method of claim 5, wherein the isotropic etching comprises dry etching using plasma, or wet etching using a chemical.

7. The method of claim 1, wherein the reducing the size of the first pattern comprises:

oxidating a surface of the first pattern; and

,

removing the oxidated portion of the first pattern.

8. The method of claim 1, wherein the reducing the size of the first pattern comprises

nitrifying a surface of the first pattern;

and,

removing the nitrified portion of the first pattern.

9. The method of claim 1, wherein the first spacer comprises a material having an etch selectivity to the first pattern and the hard mask layer.

10. The method of claim 1, wherein the second spacer comprises a material having an etch selectivity to the first pattern and the etch target layer.