SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20100167516A1
• Filed: 03/10/2010
• Published: 07/01/2010
• Est. Priority Date: 06/20/2007
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Minato, Tadaharu, Takano, Kazutoyo
• Granted Patent: US 7,955,930 B2
• Time in Patent Office: Days
• US Class Current: 438/589
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor substrate has a trench in a first main surface. An insulated gate field effect part includes a gate electrode formed in the first main surface. A potential fixing electrode fills the trench and has an expanding part expanding on the first main surface so that a width thereof is larger than the width of the trench. An emitter electrode is formed on the first main surface and insulated from the gate electrode electrically and connected to a whole upper surface of the expanding part of the potential fixing electrode. Thus, a semiconductor device capable of enhancing reliability in order to prevent an aluminum spike from generating and a manufacturing method thereof can be provided.

Claims

1. A manufacturing method of a semiconductor device comprising the steps of:

forming a trench in the main surface of a semiconductor substrate;

forming a conductive layer on said main surface so as to fill said trench;

forming a potential fixing electrode filling said trench and having an expanding part expanding on said main surface so that a width thereof is larger than that of said trench, and forming a gate electrode on said main surface by patterning said conductive layer;

forming insulation layers so as to cover said gate electrode and expose said expanding part of said potential fixing electrode; and

forming main electrodes so as to be electrically insulated from said gate electrode and connected to a whole upper surface of said expanding part of said potential fixing electrode.

2. The manufacturing method of the semiconductor device according to claim 1, wherein

said step of forming said main electrodes comprises the steps of:

forming first metal films so as to be in contact with said expanding part of said potential fixing electrode; and

forming a second metal film having a melting point lower than that of said first metal film, and more readily reacting with the material of said semiconductor substrate than said first metal film, on said first metal films.

3. The manufacturing method of the semiconductor device according to claim 2, further comprising the step of performing a heat treatment to stabilize said first and second metal films.