Semiconductor Processing Methods

• US 20100167521A1
• Filed: 03/10/2010
• Published: 07/01/2010
• Est. Priority Date: 04/11/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Liu, Junting, Ping, Er-Xuan, Takedai, Seiichi
• Granted Patent: US 7,915,168 B2
• Time in Patent Office: Days
• US Class Current: 438/597
• CPC Class Codes: C23C 18/1605 by masking
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/03616 Chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

Claims

1-25. -25. (canceled)

26. A semiconductor processing method comprising utilizing plasma-enhanced atomic layer deposition to simultaneously deposit a composition containing one or both of silicon nitride and silicon oxynitride across both a front side exposed surface and a back side exposed surface of a semiconductor substrate.

27. The method of claim 26 wherein the composition on the front side exposed surface is a first layer of the composition, and the composition across the back side exposed surface is a second layer of the composition;

and further comprising;

etching a pattern of openings extending through the first layer of the composition; and

forming conductive material within the openings.

28. The method of claim 27 wherein the forming of the conductive material comprises dipping the substrate in a plating bath.

29. The method of claim 26 wherein the composition comprises silicon nitride.

30. The method of claim 26 wherein the composition comprises silicon oxynitride.

31. A semiconductor processing method, comprising:

utilizing plasma-enhanced atomic layer deposition to simultaneously deposit a composition across both a front side exposed surface and a back side exposed surface of a semiconductor substrate;

the composition on the front side exposed surface being a first layer of the composition, and the composition across the back side exposed surface being a second layer of the composition;

forming a layer of insulative material over the first layer of the composition;

etching a pattern of openings extending through the layer of insulative material and through the first layer of the composition; and

forming conductive material within the openings.

32. The method of claim 31 wherein the forming of the conductive material comprises dipping the substrate in a plating bath.

33. The method of claim 31 wherein the composition comprises one or both of silicon nitride and silicon oxynitride.

34. A semiconductor processing method, comprising:

forming a monocrystalline silicon-containing semiconductor substrate to comprise one or more electrically conductive layers across a front side of the substrate, and to comprise one or more passivation layers over the one or more electrically conductive layers;

the semiconductor substrate comprising a back side in opposing relation to the front side;

the back side having an exposed surface, and the front side having an exposed surface comprising a surface of a passivation layer;

utilizing plasma-enhanced atomic layer deposition to simultaneously deposit a composition across the front side exposed surface and across the back side exposed surface;

the composition on the front side exposed surface being a first layer of the composition, and the composition across the back side exposed surface being a second layer of the composition;

forming a layer of insulative material over the first layer of the composition;

etching a pattern of openings extending through the layer of insulative material, through the first layer of the composition and through the one or more passivation layers to expose regions of the one or more electrically conductive layers; and

dipping the substrate in a plating bath to form conductive material within the openings.

35. The method of claim 34 wherein the semiconductor substrate remains in an orientation with the front side facing up during the recited utilization of the plasma-enhanced atomic layer deposition, and during the recited formation of the layer of insulative material.

36. The method of claim 34 wherein the composition comprises one or both of silicon nitride and silicon oxynitride.

37. A semiconductor processing method, comprising:

forming a monocrystalline silicon-containing semiconductor substrate to comprise at least one bond pad supporting layer along a front side of the substrate, and to comprise a silicon nitride passivation layer over the at least one bond pad supporting layer;

the semiconductor substrate comprising a back side in opposing relation to the front side;

the back side having an exposed surface, and the front side having an exposed surface comprising a surface of the silicon nitride passivation layer;

utilizing plasma-enhanced atomic layer deposition to simultaneously deposit insulative material across the front side exposed surface and across the back side exposed surface;

the plasma-enhanced atomic layer deposition being conducted at a temperature of from at least about 300°

C. to less than or equal to about 500°

C. to activate hydrogen in the silicon nitride passivation layer during the deposition;

etching a pattern of openings extending through the insulative material and through the silicon nitride passivation layer to expose regions of the at least one bond pad supporting layer; and

dipping the substrate in a plating bath to form conductive material within the openings, the conductive material within the openings being contacts to the semiconductor substrate front side.

38. A semiconductor processing method, comprising:

forming a monocrystalline silicon-containing semiconductor substrate to comprise one or more levels of integrated circuitry over a front side of a semiconductor substrate, and to comprise one or more bond pad supporting layers over the integrated circuitry;

the semiconductor substrate comprising a back side in opposing relation to the front side of the semiconductor substrate;

the back side having an exposed surface;

forming a passivation oxide over the one or more bond pad supporting layers;

forming a passivation nitride over the passivation oxide;

utilizing plasma-enhanced atomic layer deposition to simultaneously deposit a composition across a surface of the passivation nitride and across the back side surface;

the composition deposited across the front side surface being a first layer of the composition, and the composition deposited across the back side surface being a second layer of the composition;

the plasma-enhanced atomic layer deposition being conducted at a temperature less than or equal to about 500°

C. but high enough to thermally treat the passivation nitride to cause hydrogen migration from the passivation nitride, and;

forming a polyimide-containing layer over the first layer of the composition;

etching a pattern of openings extending through the polyimide-containing layer, through the first layer of the composition and through the passivation nitride to expose regions of the one or more bond pad supporting layers; and

dipping the substrate in a plating bath to form conductive material within the openings, the conductive material within the openings being contacts to the one or more bond pad supporting layers.