Interrupt technicques

• US 20100169528A1
• Filed: 12/30/2008
• Published: 07/01/2010
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, Amit, Zhu, Xia, Berry, Frank, Huggahalli, Ram, King, Steven, Willke, Theodore II, Bhardwaj, Nitin, Memon, Mazhar
• Granted Patent: US 8,645,596 B2
• Time in Patent Office: Days
• US Class Current: 710/263
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

Techniques are described that can be used by a message engine to notify a core or hardware thread of activity. For example, an inter-processor interrupt can be used to notify the core or hardware thread. The message engine may generate notifications in response to one or more message received from a transmitting message engine. Message engines may communicate without sharing memory space.

Claims

1. A method comprising:

receiving contents of a network protocol unit from one or more message segments at a queue associated with a message engine; and

indicating availability of contents of the queue to a core using an interrupt.

2. The method of claim 1, wherein the indicating availability of contents of the queue from the message engine to a core using an interrupt comprises generating an inter-processor interrupt.

3. The method of claim 1, wherein the indicating availability of contents of the queue from the message engine to a core using an interrupt comprises writing an MSI-X message in an MSI-X memory region.

4. The method of claim 1, further comprising:

the core programming a rate at which the message engine can interrupt the core.

5. The method of claim 4, wherein the core programming a rate comprises the core writing to a register in the coherent memory domain.

6. The method of claim 1, wherein the network protocol unit is Ethernet compliant.

7. The method of claim 1, wherein at least one of the message segments comprises:

a link layer;

a destination virtual message engine address;

a reassembly tag field;

a message segment offset field; and

a data portion.

8. The method of claim 7, wherein the queue is based on the reassembly tag field and further comprising:

a buffer in the queue based on the reassembly tag field; and

a location in the buffer to store at least one of the message segments based in part on the message segment offset field.

9. The method of claim 1, further comprising:

receiving an indication of a page fault when attempting to write contents of the one or more message segments to the queue; and

indicating the page fault to the core using a second interrupt.

10. The method of claim 9, wherein the indicating availability of contents of the queue to the core using an interrupt comprises generating an inter-processor interrupt.

11. The method of claim 1, further comprising:

receiving a second network protocol unit;

transmitting contents of the network protocol unit using one or more message segments to a second queue associated with a second message engine; and

indicating availability of contents of the second queue to a second core using a second interrupt.

12. An apparatus comprising:

a queue to receive contents of a network protocol unit from one or more message segments; and

a core; and

a message engine to indicate availability of the contents of the queue to the core using an interrupt.

13. The apparatus of claim 12, wherein to indicate availability of contents of the queue from the message engine to the core, the message engine is to generate an inter-processor interrupt.

14. The apparatus of claim 12, wherein to indicate availability of contents of the queue from the message engine to the core, the message engine is to write an MSI-X message in an MSI-X memory region.

15. The apparatus of claim 12, wherein the core programs a rate at which the message engine is permitted to interrupt the core.

16. The apparatus of claim 15, wherein the core programs a rate at which the message engine is permitted to interrupt the core by writing a register in the coherent memory domain.

17. The apparatus of claim 12, wherein at least one of the message segments comprises:

a link layer;

a destination virtual message engine address;

a reassembly tag field;

a message segment offset field; and

a data portion.

18. The apparatus of claim 17, wherein the queue is based on the reassembly tag field and further comprising:

a buffer in the queue based on the reassembly tag field; and

a location in the buffer to store at least one of the message segments based in part on the message segment offset field.

19. The apparatus of claim 12, further comprising:

a second queue, wherein;

in response to receiving an indication of a page fault when attempting to write contents of the one or more message segments to the second queue, the message engine is to indicate the page fault to the core using an interrupt.

20. The apparatus of claim 19, wherein to indicate availability of contents of the second queue to the core, the message engine is to generate an inter-processor interrupt.

21. The apparatus of claim 12, wherein the core is to regulate the rate at which the core receives interrupts.

22. A system comprising:

a storage device;

at least one core;

a network interface to receive a network protocol unit; and

first and second message engines, wherein

the first message engine is to form at least one message from contents of the network protocol unit and to transmit the at least one message to the second message engine without sharing memory space and

the second message engine is to notify one of the at least one core of availability of the message using an interrupt.

23. The system of claim 22, wherein to notify one of the at least one core of availability of the message using an interrupt, the second message engine is to generate an inter-processor interrupt.

24. The system of claim 22, wherein at least one core is to program a rate at which the second message engine is to generate interrupts.

25. The system of claim 22, wherein the message engine comprises:

a message mapper to determine a destination virtual message engine associated with the network protocol unit; and

logic to transmit content of the network protocol unit using at least one message to a queue associated with the destination virtual message engine.

26. The system of claim 22, wherein the message engine is to form at least one segment from the at least one message.