METHOD FOR PREVENTING DATA LOSS DURING SOLDER REFLOW PROCESS AND MEMORY DEVICE USING THE SAME

• US 20100169547A1
• Filed: 03/15/2009
• Published: 07/01/2010
• Est. Priority Date: 12/25/2008
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: Ou, Hsu-Ping
• Granted Patent: US 8,429,334 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification

Abstract

The invention provides a method for preventing data loss in a flash memory during a solder reflow process. The flash memory includes a plurality of memory blocks and each memory block includes a plurality of strong pages and weak pages. Preloading data is first received and stored into the strong pages of at least one of first memory block within the flash memory. Then, the flash memory is heated for the solder reflow process. Next, the preloading data is reorganized according to a trigger signal and the strong pages and weak pages of at least one of second memory block within the flash memory are provided for storing the reorganized preloading data.

Claims

1. A method for preventing data loss in a flash memory during a solder reflow process, wherein the flash memory comprises a plurality of memory blocks, each of which having a plurality of strong pages and a plurality of weak pages, comprising:

receiving a preloading data;

storing the preloading data into the strong pages of at least one first memory within the flash memory;

heating the flash memory for performing the solder reflow process; and

reorganizing the preloading data according to a trigger signal and then sequentially storing the reorganized preloading data into the strong pages and the weak pages of at least one second memory block within the flash memory.

2. The method according to claim 1, wherein the trigger signal is generated according to a recovery command.

3. The method according to claim 1, wherein the trigger signal is generated according to a state of a preset pin of the flash memory.

4. The method according to claim 1, wherein the strong pages and the weak pages are alternately arranged on the basis of a predetermined order within each memory block.

5. The method according to claim 1, wherein the storage size of each first memory block is smaller than that of each second memory block.

6. The method according to claim 5, wherein each first memory block has half the storage size with respect to that of each second memory block.

7. The method according to claim 5, further comprising:

storing the reorganized preloading data into the at least one second memory block and erasing the at least one first memory block, wherein each erased first memory block has the same storage size as each second memory block.

8. The method according to claim 1, further comprising:

determining whether the preloading data stored in the at least one second memory block is correct.

9. The method according to claim 1, wherein the programming busy time of each strong page for storing data is less than that of each weak page.

10. The method according to claim 1, wherein the flash memory is a NAND flash memory.

11. The method according to claim 1, wherein each memory block is a multi-level cell memory block.

12. A memory device, comprising:

a flash memory for storing data, wherein the flash memory comprises a plurality of memory blocks, each of which having a plurality of strong pages and a plurality of weak pages; and

a controller coupled to the flash memory for receiving a preloading data, storing the preloading data into the strong pages of at least one first memory block within the flash memory,

wherein the flash memory is heated for performing a solder reflow process and the controller reorganizes the preloading data according to a trigger signal and sequentially stores the reorganized preloading data into the strong pages and the weak pages of at least one second memory block within the flash memory.

13. The memory device according to claim 12, wherein the trigger signal is generated according to a recovery command from a host.

14. The memory device according to claim 12, wherein the trigger signal is generated according to a state of a preset pin of the flash memory.

15. The memory device according to claim 12, wherein the strong pages and the weak pages are alternately arranged on the basis of a predetermined order.

16. The memory device according to claim 12, wherein the storage size of each first memory block is smaller than that of each second memory block.

17. The memory device according to claim 16, wherein each first memory block has half the storage size with respect to that of each second memory block.

18. The memory device according to claim 16, wherein the reorganized preloading data is stored into the at least one second memory block, the controller erases the at least one first memory block, and each erased first memory block and each second memory block have the same storage size.

19. The memory device according to claim 12, wherein the controller determines whether the preloading data stored in the at least one second memory block is correct.

20. The memory device according to claim 12, wherein the programming busy time of each strong page for storing data is less than that of each weak page.