CACHE TAG MEMORY

• US 20100169578A1
• Filed: 12/31/2008
• Published: 07/01/2010
• Est. Priority Date: 12/31/2008
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: NYCHKA, Robert, TRAN, Thang M., JOHNSON, William M.
• Application Number:
  US12/347,210
• Publication Number:
  US 20100169578A1
• Time in Patent Office: Days
• US Class Current: 711/138
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system comprises tag memories and data memories. Sources use the tag memories with the data memories as a cache. Arbitration of a cache request is replayed, based on an arbitration miss and way hit, without accessing the tag memories. A method comprises receiving a cache request sent by a source out of a plurality of sources. The sources use tag memories with data memories as a cache. The method further comprises arbitrating the cache request, and replaying arbitration, based on an arbitration miss and way hit, without accessing the tag memories.

Claims

1. A system, comprising:

tag memories; and

data memories;

wherein sources use the tag memories with the data memories as a cache; and

wherein arbitration of a cache request is replayed, based on an arbitration miss and way hit, without accessing the tag memories.

2. The system of claim 1, wherein a tag memory is accessed, based on a second cache request, at the time the tag memory would have been accessed if the tag memory was accessed for replay based on the arbitration miss.

3. The system of claim 1, further comprising next registers, each next register paired with a separate tag memory.

4. The system of claim 3, wherein a next register forwards, for arbitration, the cache request;

and wherein the arbitration occurs in parallel with tag lookup.

5. The system of claim 4, further comprising replay registers, each replay register paired with a tag memory, a replay register allowing arbitration replay to bypass the tag memory paired with the replay register.

6. The system of claim 1, wherein each of the sources uses a separate tag memory.

7. The system of claim 1, wherein a tag memory and data memory are accessed concurrently based on a second cache request.

8. The system of claim 1, further comprising next registers, each next register paired with a separate set of arbitration logic.

9. The system of claim 1, wherein the data memories are organized as a banked data array.

10. The system of claim 1, wherein the data memories and the tag memories together is configurable for operation as a level 1 cache and a level 2 cache.

11. The system of claim 1, further comprising separate arbitration logic for each of the data memories.

12. A method, comprising:

receiving a cache request sent by a source out of a plurality of sources, the sources using tag memories with data memories as a cache;

arbitrating the cache request; and

replaying arbitration, based on an arbitration miss and way hit, without accessing the tag memories.

13. The method of claim 12, further comprising accessing a tag memory, based on a second cache request, at the time the tag memory would have been accessed if the tag memory was accessed for replay based on the arbitration miss.

14. The method of claim 12, further comprising updating the tag memories such that the tag memories comprise identical contents.

15. The method of claim 12, further comprising arbitrating requests for each of the data memories using separate arbitration logic.

16. The method of claim 12, wherein replaying arbitration comprises replaying arbitration, based on an arbitration miss and way hit, without accessing the tag memories, each source using a separate tag memory.

17. The method of claim 12, wherein arbitrating the cache request further comprises forwarding, for arbitration, the cache request from a next register out of a plurality of next registers, each next register paired with a separate tag memory.

18. The method of claim 17, further comprising accessing a tag memory paired with the next register in parallel with arbitrating the cache request.

19. The method of claim 18, further comprising calculating a way after arbitrating the cache request.

20. The method of claim 12, further comprising allowing arbitration replay to bypass the tag memories through a replay register.