HYBRID MEMORY DEVICE

• US 20100169604A1
• Filed: 12/30/2008
• Published: 07/01/2010
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Trika, Sanjeev N., Royer, Robert
• Granted Patent: US 8,239,613 B2
• Time in Patent Office: Days
• US Class Current: 711/170
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

A method is provided. The method includes receiving data and classifying received data in one of several tiers of data. The method also includes storing each tier of data on a different non-volatile memory device.

Claims

1. A method, comprising:

receiving data;

classifying received data in one of several tiers of data;

storing each tier of data on a different non-volatile memory device.

2. The method of claim 1, comprising classifying the received data into tier 1 data and tier 2 data.

3. The method of claim 2, comprising storing the tier 1 and tier 2 data on a first non-volatile memory device and a second non-volatile memory device respectively.

4. The method of claim 3, wherein the first non-volatile memory device comprises single-level cell (SLC) NAND flash cells, and the second non-volatile memory device comprises multi-level cell (MLC) NAND flash cells.

5. The method of claim 4, wherein the single-level cell NAND and multi-level cell NAND flash cells are on a NAND flash device.

6. The method of claim 3, wherein storing the tier 1 data comprises storing user specified writes on the first non-volatile memory device.

7. The method of claim 3, wherein storing the tier 2 data comprises storing user defined low priority writes on the second non-volatile memory device.

8. The method of claim 3, wherein the tier 2 data comprises metadata updates after lazy writes, or cache background writes for read miss insertions, or clean cache data, or non-volatile memory writes due to background relocations, or combinations thereof.

9. The method of claim 3, wherein the tier 1 data comprises dirty cache data.

10. A system, comprising:

a first non-volatile memory device;

a second non-volatile memory device; and

a memory controller coupled to the first and second non-volatile memory devices, wherein the memory controller is to split data between the first and second non-volatile memory devices.

11. The system of claim 10, wherein the first non-volatile memory device comprises single-level cell (SLC) NAND flash cells, and the second non-volatile memory device comprises multi-level cell (MLC) NAND flash cells.

12. The system of claim 11, wherein the single-level cell NAND and multi-level cell NAND flash cells are disposed on a NAND flash device.

13. The system of claim 10, wherein the first non-volatile memory device is to store user specified high priority writes.

14. The system of claim 10, wherein the second non-volatile memory device is to store at least one of user defined low priority writes, metadata updates after lazy writes, or cache background writes for read miss insertions, or clean cache data, or non-volatile memory writes due to background relocations, or combinations thereof.

15. The system of claim 10, wherein the memory controller is to split the disk cache data in accordance with a memory management policy.

16. The system of claim 10, wherein the memory controller is to split the disk cache data based upon an expected workload and disk caching policies.

17. A semiconductor device;

comprising;

a processor;

a single-level cell (SLC) NAND flash memory device coupled to the processor; and

a multi-level cell (MLC) NAND flash memory device coupled to the processor, wherein at least one of cache workload and a solid state drive workload is split between the single-level cell and multi-level cell NAND flash memory devices.

18. The semiconductor device of claim 17, wherein the split between the single-level cell and the multi-level cell NAND flash memory devices is based upon a NAND management policy.

19. The semiconductor device of claim 17, wherein the single-level cell NAND flash media and the multi-level cell NAND flash memory devices form components of an integrated memory device.

20. The semiconductor device of claim 17, wherein the processor is to receive instructions from a user to identify high priority writes and low priority writes.

21. The semiconductor device of claim 20, wherein the single-level cell (SLC) NAND flash memory device is to store the high priority writes.

22. The semiconductor device of claim 20, wherein the multi-level cell (MLC) NAND flash memory device is to store the low priority writes.

23. The semiconductor device of claim 17, further comprising a memory controller to split at least one of cache workload and a solid state drive workload into first and second disk workloads.

24. The semiconductor device of claim 17, wherein the multi-level cell (MLC) NAND flash memory device is to store at least one of cache background writes corresponding to lazy writes and cache background writes for read miss insertions.

25. A method, comprising:

splitting a workload data into tier 1 data and tier 2 data; and

transferring the tier 1 and tier 2 data to first and second non-volatile memory devices respectively, wherein an access time of the first non-volatile memory device is relatively lower than an access time of the second non-volatile memory device.

26. The method of claim 25, wherein the workload data comprises disk cache data.

27. The method of claim 25, wherein the workload data comprises solid state drive workload data.

28. The method of claim 25, wherein the workload data comprises volume spanning data.

29. The method of claim 25, wherein the first non-volatile memory device comprises a single-level cell (SLC) NAND flash memory device and the second non-volatile memory device comprises a multi-level cell (MLC) NAND flash memory device.

30. The method of claim 25, wherein splitting the workload data into tier 1 and tier 2 data comprises splitting the data based upon a NAND management policy.