Method and System for Reducing Abort Rates in Speculative Lock Elision using Contention Management Mechanisms

• US 20100169623A1
• Filed: 12/29/2008
• Published: 07/01/2010
• Est. Priority Date: 12/29/2008
• Status: Active Grant

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Dice, David
• Granted Patent: US 8,914,620 B2
• Time in Patent Office: Days
• US Class Current: 712/229
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms
• CPC Class Codes: G06F 9/528 by using speculative mechanisms

Abstract

Hardware-based transactional memory mechanisms, such as Speculative Lock Elision (SLE), may allow multiple threads to concurrently execute critical sections protected by the same lock as speculative transactions. Such transactions may abort due to contention or due to misidentification of code as a critical section. In various embodiments, speculative execution mechanisms may be augmented with software and/or hardware contention management mechanisms to reduce abort rates. Speculative execution hardware may send a hardware interrupt signal to notify software components of a speculative execution event (e.g., abort). Software components may respond by implementing concurrency-throttling mechanisms and/or by determining a mode of execution (e.g., speculative, non-speculative) for a given section and communicating that determination to the hardware speculative execution mechanisms, e.g., by writing it into a lock predictor cache. Subsequently, hardware speculative execution mechanisms may determine a preferred mode of execution for the section by reading the corresponding entry from the lock predictor cache.

Claims

1. A computer-implemented method, comprising:

attempting to execute a section of code as a transaction using a hardware transactional memory system;

the hardware transactional memory system detecting that the transaction aborted or will abort; and

in response to said detecting;

the hardware transactional memory system sending an indication of said detecting to a software mechanism;

in response to receiving the indication, the software mechanism determining a mode of execution, wherein the mode of execution comprises speculative transaction mode or non-speculative mode;

the software mechanism communicating the determined mode of execution to the hardware transactional memory system; and

the hardware transactional memory system attempting to execute the section of code using the determined mode of execution.

2. The method of claim 1, further comprising:

if the determined mode of execution comprises speculative transaction mode, the software mechanism executing a concurrency throttling mechanism over the section of code.

3. The method of claim 1, wherein said communicating comprises updating a value in a lock predictor cache.

4. The method of claim 1, wherein the indication comprises a hardware interrupt signal.

5. The method of claim 1, wherein the software mechanism comprises an interrupt handler.

6. The method of claim 1, further comprising:

in response to receiving the indication, the software mechanism sending a software interrupt signal to a signal handler; and

in response to receiving the software interrupt signal, the signal handler executing a contention management operation.

7. The method of claim 6, wherein the signal handler is associated with a region of an application that includes the section of code.

8. A system comprising:

one or more processors;

a memory coupled to the one or more processors and storing program instructions executable by one or more processors to implement a software contention management mechanism; and

a hardware transactional memory implementation;

wherein the hardware transactional memory implementation is configured to;

attempt to execute a given section of code as a respective transaction;

detect that the respective transaction aborted or will abort; and

in response to said detecting;

send an indication of said detecting to the software contention management mechanism;

wherein the software contention management mechanism is configured to;

in response to receiving an indication that a given transaction aborted or will abort, determine a mode of execution for a respective section of code, wherein the mode of execution comprises speculative transaction mode or non-speculative mode; and

communicate the determined mode of execution to the hardware transactional memory implementation;

wherein the hardware transactional memory implementation is further configured to;

in response to receiving a determined mode of execution for a given section of code, attempt to execute the section of code using the determined mode of execution.

9. The system of claim 8, wherein the software contention management mechanism is further configured to:

in response to determining that the mode of execution of the respective section of code comprises speculative transaction mode, execute a concurrency throttling mechanism over the section of code.

10. The system of claim 8, wherein said communicating comprises updating a value in a lock predictor cache.

11. The system of claim 8, wherein the indication comprises a hardware interrupt signal.

12. The system of claim 8, wherein the software contention management mechanism comprises an interrupt handler.

13. The system of claim 8,

wherein the program instructions are further executable by the one or more processors to implement a signal handler;

wherein the software contention management mechanism is further configured to;

in response to receiving the indication, send a software interrupt signal to the software interrupt handler; and

wherein in response to receiving the software interrupt signal, the signal handler is configured to;

execute a contention management operation.

14. The system of claim 13, wherein the signal handler is associated with a region of an application that includes the section of code.

15. A computer-readable storage medium storing program instructions computer-executable to implement:

receiving an indication from a hardware transactional memory system that an attempt to execute a section of code as a transaction has been aborted or will be aborted;

in response to said receiving, determining a mode of execution for the section of code, wherein the mode of execution comprises speculative transaction mode or non-speculative mode; and

communicating the determined mode of execution to the hardware transactional memory system.

16. The storage medium of claim 15, wherein the program instructions are further computer-executable to implement:

in response to determining that the mode of execution for the section of code comprises speculative transaction mode, executing a concurrency throttling mechanism over the section of code.

17. The storage medium of claim 15, wherein said communicating comprises updating a value in a lock predictor cache.

18. The storage medium of claim 15, wherein the program instructions are further computer-executable to implement an interrupt handler.

19. The storage medium of claim 15, wherein the program instructions are further computer-executable to implement:

in response to said receiving, sending a software interrupt signal to a signal handler.

20. The storage medium of claim 15, wherein the program instructions are further computer-executable to implement a signal handler configured to:

in response to said receiving a software interrupt signal, execute a contention management operation.