MEMORY DEVICE, HOST DEVICE, AND SAMPLING CLOCK ADJUSTING METHOD
First Claim
Patent Images
1. A memory device comprising:
- a nonvolatile semiconductor memory unit;
a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal when the memory controller controls sending and receiving of the command signal and the response signal through a command line to and from a host device to which the memory device is connected, sending and receiving of the data signal and the status signal through a data line to and from the host device, and receiving of a clock signal through a clock line from the host device; and
a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to the host device, the tuning pattern signal being used by the host device to adjust a phase of the clock signal for use as a sampling clock signal.
5 Assignments
0 Petitions
Accused Products
Abstract
A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.
-
Citations
20 Claims
-
1. A memory device comprising:
-
a nonvolatile semiconductor memory unit; a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal when the memory controller controls sending and receiving of the command signal and the response signal through a command line to and from a host device to which the memory device is connected, sending and receiving of the data signal and the status signal through a data line to and from the host device, and receiving of a clock signal through a clock line from the host device; and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to the host device, the tuning pattern signal being used by the host device to adjust a phase of the clock signal for use as a sampling clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A host device comprising:
-
a clock configured to generate a clock signal; a host controller configured to perform control for sending a command signal and a data signal in synchronization with the clock signal to a memory device having a nonvolatile semiconductor memory unit and being connected to the host device and for receiving from the memory device a response signal, a data signal, and a status signal in synchronization with a sampling clock signal, the sampling clock signal being the clock signal whose phase is adjusted, when the host controller controls sending and receiving of the command signal and the response signal through a command line, sending and receiving of the data signal through a data line, receiving of the status signal through a data line, and sending of the clock signal through a clock line; a sampling clock adjustment unit configured to adjust a phase of the sampling clock signal; and a host-side pattern signal storage unit configured to pre-store a tuning pattern signal having the same pattern as a tuning pattern signal sent from the memory device for adjusting the phase of the sampling clock signal. - View Dependent Claims (11, 12, 13, 14, 15)
-
-
16. A sampling clock adjusting method for a host device connected to a memory device including a nonvolatile semiconductor memory unit and configured to send and receive a command signal and a response signal to and from the memory device through a command line, send and receive a data signal to and from the memory device through a data line, receive a status signal through a data line from the memory device, and send a clock signal to the memory device through a clock line, the method comprising:
-
setting a sampling clock signal determining a sampling point at which the host device receives the data signal from the memory device in order to set an initial value of the phase of the sampling clock signal; sending from the host device to the memory device a tuning command for adjusting the phase of the sampling clock signal from the clock signal through the command line; receiving, by the host device, a first tuning pattern signal as a response signal sent through the command line from the memory device in response to the tuning command; and adjusting, by the host device, the sampling clock signal on the basis of the received first tuning pattern signal. - View Dependent Claims (17, 18, 19, 20)
-
Specification