Channel interleaver having a constellation-based unit-wise permuation module

• US 20100169722A1
• Filed: 12/30/2009
• Published: 07/01/2010
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: HFI Innovation, Inc. (MediaTek, Inc.)
• Original Assignee: MediaTek, Inc.
• Inventors: Wu, Ciou-Ping, Chang, Yu-Hao, Liao, Pei-Kai, Chen, Yih-Shen
• Granted Patent: US 8,799,735 B2
• Time in Patent Office: Days
• US Class Current: 714/701
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 27/34 Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems

Abstract

A channel interleaver comprises a novel constellation-based permutation module. The channel interleaver first receives a plurality of sets of encoded bits generated from an FEC encoder. The encoded bits are distributed into multiple subblocks and each subblock comprises a plurality of adjacent bits. A subblock interleaver interleaves each subblock and outputs a plurality of interleaved bits. The constellation-based permutation module rearranges the interleaved bits and outputs a plurality of rearranged bits. The rearranged bits are supplied to a symbol mapper such that a plurality of consecutively encoded bits in the same set of the encoded bits generated from the FEC encoder is prevented to be mapped onto the same level of bit reliability of a modulation symbol. In addition, the plurality of adjacent bits of each subblock is also prevented to be mapped onto the same level of bit reliability to achieve constellation diversity and to improve decoding performance.

Claims

1. A method for channel interleaving, comprising:

distributing a plurality of sets of encoded bits generated by a forward error correction (FEC) encoder into a first set of multiple subblocks, wherein each subblock comprises a plurality of adjacent bits;

interleaving each of the first set of subblocks and outputting a plurality of interleaved bits; and

rearranging the interleaved bits and outputting a plurality of rearranged bits, wherein the rearranged bits are supplied to a symbol mapper such that the plurality of adjacent bits within each subblock is prevented to be mapped onto the same level of bit reliability of a modulation symbol to achieve constellation diversity.

2. The method of claim 1, wherein a plurality of consecutively encoded bits in the same set of the encoded bits is also prevented to be mapped onto the same level of bit reliability of the modulation symbol.

3. The method of claim 1, wherein the rearranging further comprises:

multiplexing the interleaved bits and grouping the multiplexed interleaved bits into a second set of multiple subblocks;

partitioning each of the second set of multiple subblocks into multiple units;

selecting a number of units from the multiple units for each of the second set of multiple subblocks; and

circularly shifting a number of bits on each of the selected units for each of the second set of multiple subblocks.

4. The method of claim 1, wherein the rearranging further comprises:

partitioning the interleaved bits into multiple units;

selecting a number of units from the multiple units; and

circularly shifting a number of bits on each of the selected units for each of the first set of multiple subblocks.

5. The method of claim 3, wherein the number of units selected is determined based on modulation order, FEC block size, and position of the selected subblock.

6. The method of claim 3, wherein the number of bits shifted is determined based on modulation order, FEC block size, and position of the selected unit.

7. The method of claim 3, wherein 16QAM modulation scheme is used, wherein each of the second set of multiple subblocks is partitioned into two units, and wherein one unit out of the two units of each subblock is selected to be shifted by one bit.

8. The method of claim 3, wherein 64QAM modulation scheme is used, wherein each of the second set of multiple subblocks is partitioned into three units, and wherein two units out of the three units of each subblock are selected, and wherein one unit is shifted by one bit and the other is shifted by two bits.

9. The method of claim 1, wherein the rearranging further comprises:

multiplexing the interleaved bits and grouping the multiplexed interleaved bits into a second set of multiple subblocks;

partitioning each of the second set of multiple subblocks into multiple units;

selecting a number of units out of the multiple units; and

performing unit-wise swapping on each of the selected units for each of the second set of multiple subblocks.

10. The method of claim 1, wherein the rearranging further comprises:

partitioning each of the first set of multiple subblocks into multiple units;

selecting a number of units out of the multiple units; and

performing unit-wise swapping on each of the selected units for each of the first set of multiple subblocks.

11. The method of claim 9, wherein the number of units selected in (e) is determined based on modulation order, FEC block size, and position of the selected subblock.

12. The method of claim 9, wherein the unit-wise swapping in (f) involves swapping the i-th bit and the (N−

i+1)-th bit of a selected unit having N bits, wherein i is a running index from one to N/2.

13. The method of claim 9, wherein 16QAM modulation scheme is used, wherein each of the second set of multiple subblocks having N bits is partitioned into N/2 units, wherein each unit comprises three bits, and wherein the first bit and the last bit in each selected unit is swapped.

14. The method of claim 9, wherein 64QAM modulation scheme is used, wherein each of the second set of multiple subblocks having N bits is partitioned into N/3 units, wherein each unit comprises three bits, and wherein the first bit and the last bit in each selected unit is swapped.

15. A channel interleaver, comprising:

a bit separator that distributes a plurality of sets of encoded bits generated by a forward error correction (FEC) encoder into a first set of multiple subblocks, wherein each subblock comprises a plurality of adjacent bits;

a subblock interleaver that interleaves each of the first set of multiple subblocks and outputs a plurality of interleaved bits; and

a constellation-based permutation module that rearranges the interleaved bits and outputs a plurality of rearranged bits, wherein the rearranged bits are supplied to a symbol mapper such that the plurality of adjacent bits within each subblock is prevented to be mapped onto the same level of bit reliability of a modulation symbol to achieve constellation diversity.

16. The interleaver of claim 15, wherein a plurality of consecutively encoded bits in the same set of the encoded bits is also prevented to be mapped onto the same level of bit reliability of the modulation symbol.

17. The interleaver of claim 15, wherein the constellation-based permutation module partitions each of the first set of multiple subblocks into multiple units, selects a number of units from the multiple units, and then circularly shifts a number of bits on each of the selected units for each of the first set of multiple subblocks.

18. The interleaver of claim 15, further comprising:

a bit multiplexer for multiplexing the interleaved bits and grouping the multiplexed interleaved bits into a second set of multiple subblocks, wherein the constellation-based permutation module partitions each of the second set of multiple subblocks into multiple units, selects a number of units from the multiple units, and then circularly shifts a number of bits on each of the selected units for each of the second set of multiple subblocks.

19. The interleaver of claim 18, wherein the number of units selected is determined based on modulation order, FEC block size, and position of the selected subblock.

20. The interleaver of claim 18, wherein the number of bits shifted is determined based on modulation order, FEC block size, and position of the selected unit.

21. The interleaver of claim 18, wherein 16QAM modulation scheme is used, wherein each subblock is partitioned into two units, and wherein one unit out of the two units of each of the second set of multiple subblocks is selected to be shifted by one bit.

22. The interleaver of claim 18, wherein 64QAM modulation scheme is used, wherein each subblock is partitioned into three units, and wherein two units out of the three units of each of the second set of multiple subblocks are selected, and wherein one unit is shifted by one bit and the other is shifted by two bits.

23. The interleaver of claim 15, wherein the constellation-based permutation module partitions each subblock of the first multiple subblocks into multiple units, selects a number of units from the multiple units, and then performs unit-wise swapping on each of the selected units for each of the first set of multiple subblocks.

24. The interleaver of claim 15, further comprising:

a bit-grouping module for multiplexing the interleaved bits and grouping the multiplexed interleaved bits into a second set of multiple subblocks, wherein the constellation-based permutation module partitions each of the second set of multiple subblocks into multiple units, selects a number of units from the multiple units, and then performs unit-wise swapping on each of the selected units for each of the second set of multiple subblocks.

25. The interleaver of claim 24, wherein the number of units selected is determined based on modulation order, FEC block size, and position of the selected subblock.

26. The interleaver of claim 24, wherein the unit-wise swapping involves swapping the i-th bit and the (N−

i+1)-th bit of a selected unit having N bits, wherein i is a running index from one to N/2.

27. The interleaver of claim 24, wherein 64QAM modulation scheme is used, wherein each subblock having N bits is partitioned into N/3 units, wherein each unit comprises three bits, and wherein the first bit and the last bit in each selected unit is swapped.

28. An apparatus, comprising:

an encoder that performs forward error correction (FEC) encoding and outputs a plurality of sets of encoded bits, wherein each set of the encoded bits are distributed into a first set of multiple subblocks, and wherein each subblock comprises a plurality of adjacent bits; and

an interleaver for interleaving each of the subblocks and outputting a plurality of interleaved bits to reduce burst channel error length, wherein the interleaver is also for rearranging the interleaved bits and outputting a plurality of rearranged bits, wherein the rearranged bits are supplied to a symbol mapper such that the plurality of adjacent bits within each subblock is prevented to be mapped onto the same level of bit reliability of a modulation symbol to achieve constellation diversity.

29. The apparatus of claim 28, wherein a plurality of consecutively encoded bits in the same set of the encoded bits is also prevented to be mapped onto the same level of bit reliability of the modulation symbol.

30. The apparatus of claim 28, wherein the encoder comprises a convolutional turbo code (CTC) encoder.

31. The apparatus of claim 28, wherein the interleaver comprises a constellation-based permutation module that partitions each subblock of the first set of multiple subblocks into multiple units, selects one or more units, and circularly shifts a number of bits on each of the selected units for each subblock of the first set of multiple subblocks.

32. The apparatus of claim 28, wherein the interleaver comprises a bit-grouping module for multiplexing the interleaved bits and grouping the multiplexed interleaved bits into a second set of multiple subblocks and a constellation-based permutation module that partitions each subblock of the second set of multiple subblocks into multiple units, selects one or more units, and circularly shifts a number of bits on each of the selected units for each subblock of the second set of multiple subblocks.

33. The apparatus of claim 28, wherein the interleaver comprises a constellation-based permutation module that partitions each subblock of the first set of multiple subblocks into multiple units, selects one or more units, and performs unit-wise swapping on each of the selected units for each subblock of the first set of multiple subblocks.

34. The apparatus of claim 28, wherein the interleaver comprises a bit-grouping module for multiplexing the interleaved bits and grouping the multiplexed interleaved bits into a second set of multiple subblocks and a constellation-based permutation module that partitions each subblock of the second set of multiple subblocks into multiple units, selects one or more units, and performs unit-wise swapping on each of the selected units for each subblock of the second set of multiple subblocks.