METHOD FOR DESIGNING A HIGH PERFORMANCE ASIC (APPLICATION-SPECIFIC INTEGRATED CIRCUIT) ACCELERATOR
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Abstract
A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.
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Citations
38 Claims
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1-13. -13. (canceled)
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14. A method of making a digital signal processing (DSP) accelerator comprising:
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defining a software programmable pre-laid out macro by laying out a control logic with a fixed topology to obtain pre-laid out control logic; and defining a hardware programmable pre-laid out macro by customizing a configurable layout area and mapping a computational logic based on computation kernels for use by an application to obtain pre-laid out computational logic. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A method of making a digital signal processing (DSP) accelerator comprising:
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defining a software programmable fully pre-laid out macro by laying out a control logic with a fixed topology to obtain a fully pre laid-out control logic by laying out synchronization, control, and data routing logic with a fixed topology; defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area and mapping a computational logic based on computation kernels for use by an application to obtain a partially pre-laid out computational logic; and verifying and characterizing design behavior and timing of the fully pre-laid out control logic. - View Dependent Claims (27, 28)
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29. A digital signal processing (DSP) accelerator comprising:
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a software programmable pre-laid out control logic; and a hardware programmable pre-laid out computational logic based on computation kernels for use by an application. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38)
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Specification