Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate

• US 20100171194A1
• Filed: 03/18/2010
• Published: 07/08/2010
• Est. Priority Date: 10/29/2005
• Status: Active Grant

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac Limited
• Inventors: Lin, Yaojian
• Granted Patent: US 8,791,006 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer.

Claims

1. A method of making a semiconductor device, comprising:

forming a polymer matrix composite substrate;

forming a first insulating layer over a first surface of the polymer matrix composite substrate;

forming a first conductive layer over the first insulating layer;

forming a second insulating layer over the first insulating layer and first conductive layer;

forming a second conductive layer over the second insulating layer and first conductive layer;

forming a third insulating layer over the second insulating layer and second conductive layer;

removing a portion of the third insulating layer to expose the second conductive layer; and

forming a bump over the second conductive layer.

2. The method of claim 1, wherein forming the polymer matrix composite substrate includes:

providing a chase mold having first and second plates;

applying a first releasable layer over the first plate;

forming a metal carrier over the second plate;

applying a second releasable layer over the metal carrier; and

depositing an encapsulant material between the first and second plates of the chase mold.

3. The method of claim 1, further including forming a third conductive layer between the first conductive layer and second conductive layer.

4. The method of claim 1, further including forming a fourth insulating layer over a second surface of the polymer matrix composite substrate, opposite the first surface of the polymer matrix composite substrate.

5. The method of claim 1, further including forming a fourth insulating layer over the first insulating layer prior to forming the first conductive layer.

6. The method of claim 1, wherein the second conductive layer is wound to exhibit inductive properties.

7. A method of making a semiconductor device, comprising:

forming a molded substrate;

forming a first conductive layer over the molded substrate;

forming a first insulating layer over the molded substrate and first conductive layer;

forming a second conductive layer over the first insulating layer and first conductive layer;

forming a second insulating layer over the first insulating layer and second conductive layer; and

forming an interconnect structure over the second conductive layer.

8. The method of claim 7, wherein forming the molded substrate includes:

providing a chase mold having first and second plates;

applying a first releasable layer over the first plate;

applying a second releasable layer over the over the second plate; and

depositing an encapsulant material between the first and second plates of the chase mold.

9. The method of claim 7, further including forming a third conductive layer between the first conductive layer and second conductive layer.

10. The method of claim 7, further including:

forming a third insulating layer over a first surface of the molded substrate prior to forming the first conductive layer; and

forming a fourth insulating layer over a second surface of the molded substrate, opposite the first surface of the molded substrate.

11. The method of claim 7, further including:

forming a third insulating layer over a first surface of the molded substrate prior to forming the first conductive layer; and

forming a fourth insulating layer over the third insulating layer.

12. The method of claim 7, wherein the second conductive layer is wound to exhibit inductive properties.

13. The method of claim 7, wherein the interconnect structure includes a bump or bond wire.

14. A method of making a semiconductor device, comprising:

forming a polymer matrix composite substrate;

forming an inductor over the polymer matrix composite substrate; and

forming an interconnect structure over the inductor.

15. The method of claim 14, wherein forming the polymer matrix composite substrate includes:

providing a chase mold having first and second plates;

applying a first releasable layer over the first plate;

applying a second releasable layer over the second plate; and

depositing an encapsulant material between the first and second plates of the chase mold.

16. The method of claim 14, further including:

forming a first conductive layer over the polymer matrix composite substrate;

forming a first insulating layer over the polymer matrix composite substrate and first conductive layer;

forming a second conductive layer over the first insulating layer and first conductive layer;

forming a second insulating layer over the first insulating layer and second conductive layer; and

forming the interconnect structure over the second conductive layer.

17. The method of claim 16, further including forming a third conductive layer between the first conductive layer and second conductive layer.

18. The method of claim 16, further including:

forming a third insulating layer over a first surface of the polymer matrix composite substrate prior to forming the first conductive layer; and

forming a fourth insulating layer over a second surface of the polymer matrix composite substrate, opposite the first surface of the polymer matrix composite substrate.

19. The method of claim 16, further including:

forming a third insulating layer over a first surface of the polymer matrix composite substrate prior to forming the first conductive layer; and

forming a fourth insulating layer over the third insulating layer.

20. A semiconductor device, comprising:

a polymer matrix composite substrate;

a first conductive layer formed over the polymer matrix composite substrate;

a first insulating layer formed over the polymer matrix composite substrate and first conductive layer;

a second conductive layer formed over the first insulating layer and first conductive layer;

a second insulating layer formed over the first insulating layer and second conductive layer; and

an interconnect structure formed over the second conductive layer.

21. The semiconductor device of claim 20, further including a third conductive layer formed between the first conductive layer and second conductive layer.

22. The semiconductor device of claim 20, further including:

a third insulating layer formed over a first surface of the polymer matrix composite substrate; and

a fourth insulating layer formed over a second surface of the polymer matrix composite substrate, opposite the first surface of the polymer matrix composite substrate.

23. The semiconductor device of claim 20, further including:

a third insulating layer formed over a first surface of the polymer matrix composite substrate; and

a fourth insulating layer formed over the third insulating layer.

24. The semiconductor device of claim 20, wherein the second conductive layer is wound to exhibit inductive properties.

25. The semiconductor device of claim 20, wherein the interconnect structure includes a bump or bond wire.