Isolation Structure for Stacked Dies

• US 20100171197A1
• Filed: 01/05/2009
• Published: 07/08/2010
• Est. Priority Date: 01/05/2009
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chang, Hung-Pin, Hsu, Kuo-Ching, Chiou, Wen-Chih, Chen, Chen-Shien
• Application Number:
  US12/348,622
• Publication Number:
  US 20100171197A1
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon via. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon via. The isolation film is thinned to re-expose the through-silicon via, and conductive elements are formed on the through-silicon via. The conductive element may be, for example, a solder ball or a conductive pad. The conductive pad may be formed by depositing a seed layer and an overlying mask layer. The conductive pad is formed on the exposed seed layer. Thereafter, the mask layer and the unused seed layer may be removed.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a circuit side and a backside opposite the circuit side;

through-silicon vias extending through the semiconductor substrate, each of the through-silicon vias having a protruding portion from the backside of the semiconductor substrate;

an isolation film on the backside of the semiconductor substrate between adjacent ones of the through-silicon vias, the isolation film not extending beyond the top of the protruding portion of each of the through-silicon vias; and

a conductive element on the protruding portion of each of the through-silicon vias.

2. The semiconductor device of claim 1, wherein the conductive element comprises a conducting seed layer on the protruding portion of each of the through-silicon vias and a conductive pad on the conducting seed layer.

3. The semiconductor device of claim 2, wherein the conducting seed layer extends over a portion of the isolation film.

4. The semiconductor device of claim 2, wherein the conductive pad comprises copper.

5. The semiconductor device of claim 1, wherein the isolation film extends along sidewalls of the protruding portion of each of the through-silicon vias.

6. The semiconductor device of claim 1, wherein the conductive element comprises a solder ball.

7. The semiconductor device of claim 1, further comprising conductive bumps on the circuit side of the semiconductor substrate.

8. A method of forming a semiconductor device, the method comprising:

providing a semiconductor substrate having a through-silicon via extending from a circuit side partially through the semiconductor substrate;

thinning a backside of the semiconductor substrate such that the through-silicon via protrudes from the backside of the semiconductor substrate;

forming an isolation film over the backside of the semiconductor substrate and the through-silicon via;

thinning the isolation film such that the through-silicon via is exposed; and

forming a conductive element on the through-silicon via.

9. The method of claim 8, wherein the forming the conductive element comprises forming a solder ball on the through-silicon via.

10. The method of claim 8, wherein the forming the conductive element comprises:

forming a seed layer over the through-silicon via; and

forming a metal pad over the seed layer.

11. The method of claim 8, wherein a liner is interposed between the through-silicon via and the semiconductor substrate and further comprising removing the liner from over the through-silicon via.

12. The method of claim 11, wherein the removing the liner is performed after the forming the isolation film.

13. The method of claim 11, wherein the isolation film has a planar surface.

14. A method of forming a semiconductor device, the method comprising:

providing a semiconductor substrate, the semiconductor substrate having a first side and a second side opposite the first side, the semiconductor substrate having a through-silicon via extending from the first side partially through the semiconductor substrate;

exposing the through-silicon via such that at least a portion of the through-silicon via protrudes from the second side of the semiconductor substrate;

forming a dielectric layer over the second side of the semiconductor substrate;

forming a patterned mask over the dielectric layer, the dielectric layer over the through-silicon via being exposed; and

removing the dielectric layer over the through-silicon via.

15. The method of claim 14, further comprising forming a conductive element over the through-silicon via.

16. The method of claim 15, wherein the conductive element comprises solder.

17. The method of claim 14, further comprising removing the patterned mask after the removing the dielectric layer.

18. The method of claim 14, wherein a liner is interposed between the through-silicon via and the semiconductor substrate.

19. The method of claim 18, further comprising removing the liner after the forming the patterned mask.

20. The method of claim 18, wherein the liner extends along sidewalls of the portion of the through-silicon via protruding from the second side of the substrate.