STACKABLE SEMICONDUCTOR DEVICE PACKAGES

• US 20100171207A1
• Filed: 08/25/2009
• Published: 07/08/2010
• Est. Priority Date: 01/07/2009
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: CHU, Chi-Chih, CHEN, Jen-Chuan, WENG, Cheng-Yi, Shen, Chi-Chih, CHANG, Wen-Hsiung
• Granted Patent: US 8,012,797 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45565 Single coating layer
• CPC Class Codes: H01L 2224/45664 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.

Claims

1. A manufacturing method, comprising:

providing a substrate including an upper surface and contact pads disposed adjacent to the upper surface of the substrate;

applying a first electrically conductive material to the upper surface of the substrate to form first conductive bumps disposed adjacent to respective ones of the contact pads;

electrically connecting a semiconductor device to the upper surface of the substrate;

applying a molding material to the upper surface of the substrate to form a molded structure covering the first conductive bumps and the semiconductor device, the molded structure including an upper surface, upper ends of the first conductive bumps being recessed below the upper surface of the molded structure;

forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps;

applying, through the openings, a second electrically conductive material to the upper ends of the first conductive bumps to form second conductive bumps; and

forming cutting slits extending through the molded structure and the substrate.

2. The manufacturing method of claim 1, wherein forming the openings is carried out using laser ablation.

3. The manufacturing method of claim 1, wherein applying the second electrically conductive material includes:

depositing conductive balls on respective ones of the first conductive bumps; and

reflowing the conductive balls and the first conductive bumps to form the second conductive bumps,

wherein upper ends of the second conductive bumps are recessed below the upper surface of the molded structure.

4. The manufacturing method of claim 1, wherein applying the second electrically conductive material includes:

depositing a solder paste on the first conductive bumps; and

reflowing the solder paste and the first conductive bumps to form the second conductive bumps,

wherein upper ends of the second conductive bumps are recessed below the upper surface of the molded structure.

5. The manufacturing method of claim 1, wherein the openings define covered portions and uncovered portions of the second conductive bumps, at least one of the openings having a central depth D_C and a peripheral depth D_P, the central depth D_C corresponding to a distance between the upper surface of the molded structure and an upper end of a respective one of the second conductive bumps, the peripheral depth D_P corresponding to a distance between the upper surface of the molded structure and a boundary between a covered portion and an uncovered portion of the respective one of the second conductive bumps, the peripheral depth D_P being greater than the central depth D_C, such that D_P=cD_C, and c≧

1.5.

6. The manufacturing method of claim 5, wherein c is in the range of 1.5 to 4.5.

7. The manufacturing method of claim 5, wherein the molded structure has a thickness H_P, the respective one of the second conductive bumps has a width W_C, such that H_P≧

D_P≧

0.4W_C.

8. The manufacturing method of claim 7, wherein the at least one of the openings has a width W_U adjacent to the upper surface of the molded structure, such that W_U>

W_C.

9. A manufacturing method, comprising:

providing a first semiconductor device package including

a substrate unit including an upper surface,

first connecting elements extending upwardly from the upper surface of the substrate unit, at least one of the first connecting elements having a width W_C,

a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit, and

a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package body including an upper surface and defining openings disposed adjacent to the upper surface of the package body, upper ends of the first connecting elements being recessed below the upper surface of the package body, the openings at least partially exposing respective ones of the first connecting elements, at least one of the openings having a width W_U adjacent to the upper surface of the package body, such that W_U>

W_C;

providing a second semiconductor device package including a lower surface and second connecting elements extending downwardly from the lower surface of the second semiconductor device package;

positioning the second semiconductor device package with respect to the first semiconductor device package, such that the second connecting elements are adjacent to respective ones of the first connecting elements; and

merging respective pairs of the first connecting elements and the second connecting elements to form stacking elements extending through respective ones of the openings of the package body and electrically connecting the first semiconductor device package and the second semiconductor device package.

10. The manufacturing method of claim 9, wherein a distance between nearest-neighbor ones of the first connecting elements corresponds to a pitch P, such that P≧

W_U>

W_C.

11. The manufacturing method of claim 9, wherein the openings of the package body define covered portions and uncovered portions of the first connecting elements, at least one of the openings has a width W_L adjacent to a boundary between a covered portion and an uncovered portion of a respective one of the first connecting elements, the width W_U is greater than the width W_L, such that W_U=aW_L, and a is in the range of 1.1 to 1.7.

12. The manufacturing method of claim 11, wherein W_C≧

W_L≧

0.8W_C.

13. The manufacturing method of claim 9, wherein at least one of the stacking elements includes:

a lower portion disposed adjacent to the upper surface of the substrate unit and having a width W_SL; and

an upper portion disposed adjacent to the lower surface of the second semiconductor device package and having a width W_SU, such that W_SU≧

W_SL.

14. The manufacturing method of claim 13, wherein the width W_SU is greater than the width W_SL, such that W_SU=fW_SL, and f is in the range of 1.05 to 1.7.

15. The manufacturing method of claim 13, wherein the width W_SU is greater than the width W_SL, such that a lateral boundary of the at least one of the stacking elements defines a taper angle α

, and α

is in the range of 2°

to 30°

.

16. The manufacturing method of claim 15, wherein α

is in the range of 5°

to 20°

.

17. A stacked package assembly, comprising:

a first semiconductor device package including

a substrate unit including an upper surface,

a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit, and

a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package body including an upper surface and defining openings disposed adjacent to the upper surface of the package body;

a second semiconductor device package disposed adjacent to the upper surface of the package body, the second semiconductor device package including a lower surface; and

stacking elements vertically extending through respective ones of the openings of the package body and electrically connecting the first semiconductor device package and the second semiconductor device package, at least one of the stacking elements corresponding to a pair of fused conductive bumps and having a lateral extent that is substantially uniform over a vertical extent of the at least one of the stacking elements.

18. The stacked package assembly of claim 17, wherein the lateral extent of the at least one of the stacking elements exhibits a standard deviation that is no greater than 20 percent over the vertical extent of the at least one of the stacking elements.

19. The stacked package assembly of claim 17, wherein the at least one of the stacking elements includes:

an upper portion disposed adjacent to the lower surface of the second semiconductor device package and having a width W_SU;

a lower portion that is at least partially covered by the package body and having a width W_SL; and

a middle portion disposed between the upper portion and the lower portion and having a width W_SM, such that W_SM≧

0.8×

min(W_SU, W_SL).

20. The stacked package assembly of claim 19, wherein the lower portion is disposed adjacent to the upper surface of the substrate unit, and the upper portion is at least partially disposed within a respective one of the openings and is spaced apart from the package body.