Three dimensional structure memory

• US 20100171224A1
• Filed: 07/04/2009
• Published: 07/08/2010
• Est. Priority Date: 04/04/1997
• Status: Abandoned Application

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: Elm 3DS Innovations LLC
• Inventors: Leedy, Glenn J.
• Application Number:
  US12/497,652
• Publication Number:
  US 20100171224A1
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. An integrated circuit structure comprising:

a first substrate comprising a first surface having interconnect contacts; and

a second substrate comprising a first surface and a second surface each having interconnect contacts, therein the second surface is opposite the first surface;

a third substrate comprising a first surface having interconnect contacts;

a plurality of vertically aligned bonds forming signal paths between the interconnect contacts of the surfaces of the second substrate and the interconnect contacts of the first surfaces of the first and third substrates;

wherein at least one of said bonds forming a signal path between the interconnect contacts of the first surfaces of the first and second substrates not aligned to one of said bonds forming a signal path between the interconnect contacts of the second surface of the second substrate and the first surface of the third substrate, wherein at least one of the substrates is thinned to provide at least one thinned substrate, wherein a second surface opposite the first surface of said at least one thinned substrate is a polished surface.

5. The integrated circuit structure of claim 1, wherein at least one of the first and second substrates is at least one of the following:

less than about 10 microns in thickness;

substantially flexible;

comprises a dielectric layer with a tensile stress of about 5×

10⁸ dynes/cm² or less.

9. The integrated circuit structure of claim 1, wherein, the polished surface is a CMP polished surface.

13. The integrated circuit structure of claim 1, wherein at least one of the substrates is substantially flexible.

2. An integrated circuit structure comprising:

a first substrate having topside and bottomside surfaces, wherein the topside surface of the first substrate has interconnect contacts;

a second substrate having topside and bottomside surfaces, wherein the topside and the bottomside surfaces of the second substrate have interconnect contacts;

a third substrate having topside and bottomside surfaces, wherein the bottomside surface of the third substrate has interconnect contacts;

a plurality of bonds between the bottomside surface of the second substrate and the topside surface of the first substrate;

vertically aligned conductive paths formed between the interconnect contacts of the topside of the first substrate and the interconnect contacts of the bottomside of the second substrate, and vertically aligned conductive paths formed between the interconnect contacts of the topside of the second substrate and the interconnect contacts of the bottomside of the third substrate, the conductive paths providing electrical connections between at least two of the first, second and third substrates;

wherein at least one of said conductive paths formed between the interconnect contacts of the topside surface of the first substrate and the bottomside surface of the second substrate are not vertically aligned to one of said conductive paths formed between the interconnect contacts of the topside of the second substrate and the interconnect contacts of the bottomside of the third substrate, wherein at least one the of the substrates is thinned to provide at least one thinned substrate, and wherein the bottomside surface of said at least one thinned substrate is a polished surface.

6. The integrated circuit structure of claim 2, wherein at least one of the first and second substrates is at least one of the following:

less than about 10 microns in thickness;

substantially flexible;

comprises a dielectric layer with a tensile stress of about 5×

10⁸ dynes/cm² or less.

10. The integrated circuit structure of claim 2, wherein the polished surface is a CMP polished surface.

14. The integrated circuit structure of claim 2, wherein at least one of the substrates is substantially flexible.

3. An integrated circuit structure comprising:

a first substrate having a first and a second surface, wherein said second surface is opposite to said first surface;

a second substrate having a first and a second surface, wherein said second surface is opposite to said first surface;

a third substrate having a first and a second surface, wherein said second surface is opposite to said first surface;

a plurality of bondformed contacts between the first surface of the first substrate and the first surface of the second substrate and between the second surface of the second substrate and the first surface of the third substrate;

wherein at least two of said contacts are selected from a group consisting of;

a conductive signal path;

a conductive contact; and

a non-conductive contact; and

wherein at least one of said contacts between the first and second substrates does not vertically align with one of said contacts between the second and third substrates, wherein at least one of the substrates is thinned to provide at least one thinned substrate, and wherein the second surface of said at least one thinned substrate is a polished surface.

7. The integrated circuit structure of claim 3, wherein at least one of the first and second substrates is at least one of the following:

less than about 10 microns in thickness;

substantially flexible;

comprises a dielectric layer with a tensile stress of about 5×

10⁸ dynes/cm² or less.

11. The integrated circuit structure of claim 3, wherein the polished surface is a CMP polished surface.

15. The integrated circuit structure of claim 3, wherein at least one of the substrates is substantially flexible.

4. An integrated circuit structure comprising:

a first substrate having a first and a second surface, wherein said second surface is opposite to said first surface;

a second substrate having a first and a second surface, wherein said second surface is opposite to said first surface;

a third substrate having a first and a second surface, wherein said second surface is opposite to said first surface;

a plurality of bondformed contacts between the second surface of the first substrate and the first surface of the second substrate and between the second surface of the second substrate and the first surface of the third substrate;

wherein at least two of said contacts are selected from a group consisting of;

a conductive signal path;

a conductive contact; and

a non-conductive contact; and

wherein at least one of said contacts between the first and second substrates does not vertically align with one of said contacts between the second and third substrates, wherein at least one of the substrates is thinned to provide at least one thinned substrate, and wherein the second surface of said at least one thinned substrate is a polished surface.

8. The integrated circuit structure of claim 4, wherein at least one of the first and second substrates is at least one of the following:

less than about 10 microns in thickness;

substantially flexible;

comprises a dielectric layer with a tensile stress of about 5×

10⁸ dynes/cm² or less.

12. The integrated circuit structure of claim 4, wherein the polished surface is a CMP polished surface.

16. The integrated circuit structure of claim 4, wherein at least one of the substrates is substantially flexible.