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Processor Arrays Made of Standard Memory Cells

  • US 20100172190A1
  • Filed: 09/17/2008
  • Published: 07/08/2010
  • Est. Priority Date: 09/18/2007
  • Status: Active Grant
First Claim
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1. A circuit to concurrently evaluate sum-of-products functions of a given input vector and a multitude of stored vectors, the circuit comprising a plurality of memory cells interconnected by a plurality of bit lines and a sense amplifier connected to said plurality of bit lines to measure a voltage level on said bit lines, wherein the stored vectors are stored in said memory cells, the input vector is introduced on said bit lines of at least a portion of said plurality of memory cells, the sum-of-products being evaluated by said sense amplifier measuring a voltage level on said bit lines;

  • and where the circuit also performs standard memory functions.

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