Processor Arrays Made of Standard Memory Cells
First Claim
1. A circuit to concurrently evaluate sum-of-products functions of a given input vector and a multitude of stored vectors, the circuit comprising a plurality of memory cells interconnected by a plurality of bit lines and a sense amplifier connected to said plurality of bit lines to measure a voltage level on said bit lines, wherein the stored vectors are stored in said memory cells, the input vector is introduced on said bit lines of at least a portion of said plurality of memory cells, the sum-of-products being evaluated by said sense amplifier measuring a voltage level on said bit lines;
- and where the circuit also performs standard memory functions.
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Accused Products
Abstract
Standard memory circuits are used for executing a sum-of-products function between data stored in the memory and data introduced into the memory. The sum-of-products function is executed in a manner substantially similar to a standard memory read operation. The memory circuits are standard or slightly modified SRAM and DRAM cells, or computing memory arrays (CAMs).
427 Citations
11 Claims
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1. A circuit to concurrently evaluate sum-of-products functions of a given input vector and a multitude of stored vectors, the circuit comprising a plurality of memory cells interconnected by a plurality of bit lines and a sense amplifier connected to said plurality of bit lines to measure a voltage level on said bit lines, wherein the stored vectors are stored in said memory cells, the input vector is introduced on said bit lines of at least a portion of said plurality of memory cells, the sum-of-products being evaluated by said sense amplifier measuring a voltage level on said bit lines;
- and where the circuit also performs standard memory functions.
- View Dependent Claims (2, 3, 4, 5)
- 6. The use of standard memory circuits for executing a sum-of-products function between data stored in said memory and data introduced into said memory in a manner substantially similar to a standard memory read operation.
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9. A circuit to concurrently evaluate sum-of-products function of a given input vector and a multitude of stored vectors, comprising a standard DRAM array, where stored vectors are stored in DRAM cells in said DRAM array, inputs vectors are introduced on Read-Write lines of at least part of said DRAM array, and sum-of-products is evaluated by sensing the voltage level on bit lines of said DRAM array;
- and where said DRAM array also retains standard DRAM functionality.
- View Dependent Claims (10, 11)
Specification