BALANCED SENSE AMPLIFIER FOR SINGLE ENDED BITLINE MEMORY ARCHITECTURE
First Claim
1. A system comprising, a single-ended bit line memory device, said memory device comprising;
- a balanced differential sense amplifier;
a first input of said balanced differential sense amplifier coupled to a bit line of a selected memory bank;
a second input of said balanced differential sense amplifier coupled to a corresponding single ended bit line from a unselected memory bank;
a voltage adder/subtractor; and
a coupler having a first terminal connected to said voltage adder/subtractor and the second terminal connected to the second input of the balanced differential sense amplifier.
1 Assignment
0 Petitions
Accused Products
Abstract
A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell.
-
Citations
20 Claims
-
1. A system comprising, a single-ended bit line memory device, said memory device comprising;
-
a balanced differential sense amplifier; a first input of said balanced differential sense amplifier coupled to a bit line of a selected memory bank; a second input of said balanced differential sense amplifier coupled to a corresponding single ended bit line from a unselected memory bank; a voltage adder/subtractor; and a coupler having a first terminal connected to said voltage adder/subtractor and the second terminal connected to the second input of the balanced differential sense amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A single-ended bit line memory device comprising a balanced differential sense amplifier;
-
a first input of said balanced differential sense amplifier coupled to a bit line of a selected memory bank; a second input of said balanced differential sense amplifier coupled to a corresponding single ended bit line from the unselected memory bank; a voltage adder/subtractor; and a coupler having a first terminal connected to said voltage adder/subtractor and the second terminal connected to the second input of the balanced differential sense amplifier. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
-
15. A method for sensing the voltage level in a single ended bit line memory device, the method comprising generating a voltage step whenever a memory bank is selected;
- and
coupling said voltage step to the complementary node of a balanced sense amplifier receiving the sense bit from the selected memory cell. - View Dependent Claims (16, 17, 18, 19, 20)
- and
Specification