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BALANCED SENSE AMPLIFIER FOR SINGLE ENDED BITLINE MEMORY ARCHITECTURE

  • US 20100172199A1
  • Filed: 11/11/2009
  • Published: 07/08/2010
  • Est. Priority Date: 11/11/2008
  • Status: Active Grant
First Claim
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1. A system comprising, a single-ended bit line memory device, said memory device comprising;

  • a balanced differential sense amplifier;

    a first input of said balanced differential sense amplifier coupled to a bit line of a selected memory bank;

    a second input of said balanced differential sense amplifier coupled to a corresponding single ended bit line from a unselected memory bank;

    a voltage adder/subtractor; and

    a coupler having a first terminal connected to said voltage adder/subtractor and the second terminal connected to the second input of the balanced differential sense amplifier.

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