BALANCED SENSE AMPLIFIER FOR SINGLE ENDED BITLINE MEMORY ARCHITECTURE

• US 20100172199A1
• Filed: 11/11/2009
• Published: 07/08/2010
• Est. Priority Date: 11/11/2008
• Status: Active Grant

• Current Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: Mishra, Anand Kumar, Rawat, Harsh
• Granted Patent: US 8,144,537 B2
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell.

Claims

1. A system comprising, a single-ended bit line memory device, said memory device comprising;

a balanced differential sense amplifier;

a first input of said balanced differential sense amplifier coupled to a bit line of a selected memory bank;

a second input of said balanced differential sense amplifier coupled to a corresponding single ended bit line from a unselected memory bank;

a voltage adder/subtractor; and

a coupler having a first terminal connected to said voltage adder/subtractor and the second terminal connected to the second input of the balanced differential sense amplifier.

2. The system as claimed in claim 1, wherein said coupler is a capacitor.

3. The system as claimed in claim 2, wherein said coupler is a device capacitance of a MOS device.

4. The system as claimed in claim 2, wherein said coupler is the device capacitance of a poly to n-well device.

5. The system as claimed in claim 1, wherein the voltage adder/subtractor comprises a logic gate that provides an active level change to said coupler when the desired memory bank is selected.

6. The system as claimed in claim 1, wherein said coupler is a pass gate.

7. The system as claimed in claim 6, wherein said pass gate is a MOS switch.

8. A single-ended bit line memory device comprising a balanced differential sense amplifier;

a first input of said balanced differential sense amplifier coupled to a bit line of a selected memory bank;

a second input of said balanced differential sense amplifier coupled to a corresponding single ended bit line from the unselected memory bank;

a voltage adder/subtractor; and

a coupler having a first terminal connected to said voltage adder/subtractor and the second terminal connected to the second input of the balanced differential sense amplifier.

9. The single-ended bit line memory device as claimed in claim 8, wherein said coupler is a capacitor.

10. The single-ended bit line memory device as claimed in claim 9, wherein said coupler is a device capacitance of a MOS device.

11. The single-ended bit line memory device as claimed in claim 9, wherein said coupler is the device capacitance of a poly to n-well device.

12. The single-ended bit line memory device as claimed in claim 8, wherein said voltage adder/subtractor comprises a logic gate that provides an active level change to said coupler when the desired memory bank is selected.

13. The single-ended bit line memory device as claimed in claim 8, wherein said coupler is a pass gate.

14. The single-ended bit line memory device as claimed in claim 13, wherein said pass gate is a MOS switch.

15. A method for sensing the voltage level in a single ended bit line memory device, the method comprising generating a voltage step whenever a memory bank is selected;

and

coupling said voltage step to the complementary node of a balanced sense amplifier receiving the sense bit from the selected memory cell.

16. The method as claimed in claim 15, wherein the added/subtracted voltage is generated by a charge sharing mechanism on the internal sensing nodes of the sense amplifier.

17. The method as claimed in claim 15, further comprising a voltage adder/subtractor that comprises a logic gate that provides an active level change to a coupler when the memory bank is selected.

18. The method as claimed in claim 17, wherein said coupler is a pass gate.

19. The method as claimed in claim 17, wherein said coupler is a capacitor.

20. The method as claimed in claim 17, wherein said coupler is a device capacitance of a MOS device.