Three dimensional structure memory

• US 20100173453A1
• Filed: 07/04/2009
• Published: 07/08/2010
• Est. Priority Date: 04/04/1997
• Status: Active Grant

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J.
• Granted Patent: US 8,288,206 B2
• Time in Patent Office: Days
• US Class Current: 438/109
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A method of making a circuit structure comprising:

forming a first substrate with a first surface having interconnect contacts;

forming a second substrate with a first surface having interconnect contacts and a second surface, wherein the second surface is opposite said first surface of the second substrate;

bonding the first surface of the first substrate to the first surface of the second substrate;

thinning the second substrate from the second surface;

performing Chemical Mechanical Polishing of the second surface of the second substrate; and

,

forming at least one vertical interconnection between one of the interconnect contacts of the first substrate and one of the interconnect contacts of the second substrate.

2. The method of claim 1, further comprising:

forming a third substrate with a first surface having interconnect contacts; and

bonding the first surface of the third substrate to the second surface of the second substrate.

3. The method of claim 2, further comprising the step of forming a connection between the at least one vertical interconnection and at least one of the interconnect contacts of the first surface of the third substrate.

4. The method of claim 1, further comprising forming of interconnect contacts at least one of on, within and beneath the second surface of the second substrate.

5. The method of claim 1, wherein the bonding of the first surface of the first substrate to the first surface of the second substrate is performed before the thinning and polishing of the second surface of the second substrate.

6. The method of claim 1, wherein the bonding of the first surface of the first substrate to the first surface of the second substrate is performed after the thinning of the second substrate.

7. The method of claim 1, wherein said at least one vertical interconnection is formed through the second substrate, in whole or in part from the first surface of the second substrate, or in whole or in part from the second surface of the second substrate.

8. The method of claim 1, further comprising thinning the second substrate to a thickness of less than 50 microns.

9. A method of making a circuit structure comprising:

forming a first substrate with a first surface having interconnect contacts;

forming a second substrate with a first surface having interconnect contacts and a second surface, wherein the second surface is opposite said first surface of the second substrate;

bonding the first surface of the first substrate to the first surface of the second substrate;

thinning the second substrate from the second surface;

performing Chemical Mechanical Polishing of the second surface of the second substrate;

depositing a dielectric on the second surface of the second substrate; and

,

forming at least one vertical interconnection between one of the interconnect contacts of the first substrate and one of the interconnect contacts of the second substrate.

10. The method of claim 9, further comprising:

forming a third substrate with a first surface having interconnect contacts; and

bonding the first surface of the third substrate to the second surface of the second substrate.

11. The method of claim 10, further comprising the step of forming at least one vertical interconnection between at least one of:

interconnect contacts of the first and the second substrates;

interconnect contacts of the first and the third substrates; and

interconnect contacts of the second and the third substrates.

12. The method of claim 9, further comprising forming of interconnect contacts at least one of on, within and beneath the second surface of the second substrate.

13. The method of claim 9, wherein the bonding of the first surface of the first substrate to the first surface of the second substrate is performed before the thinning of the second substrate.

14. The method of claim 9, wherein the bonding of the first surface of the first substrate to the first surface of the second substrate is performed after the thinning of the second substrate.

15. The method of claim 9, wherein said at least one vertical interconnection is formed through the second substrate one of in whole or in part from the first surface of the second substrate and one of in whole or in part from the second surface of the second substrate.

16. The method of claim 9, further comprising thinning the second substrate to a thickness of less than 50 microns.

17. A method of making a circuit structure comprising:

forming a first substrate with a first surface having interconnections;

forming a second substrate with a first surface having interconnections and a second surface, wherein the second surface is opposite said first surface of the second substrate;

bonding the first surface of the first substrate to the first surface of the second substrate;

thinning the second substrate from the second surface;

performing Chemical Mechanical Polishing of the second surface of the second substrate; and

,

forming at least one vertical interconnection between one of the interconnections of the first substrate and one of the interconnections of the second substrate, wherein the said at least one vertical interconnection is formed in whole or in part from the first surface of the second substrate, or in whole or in part from the second surface of the second substrate.

18. The method of claim 17, further comprising:

forming a third substrate with a first surface having interconnections; and

bonding the first surface of the third substrate to the second surface of the second substrate.

19. The method of claim 18, further comprising the step of forming a connection between the at least one vertical interconnection and at least one of the interconnections of first surface of the third substrate.

20. The method of claim 17, further comprising forming of interconnections at least one of on, within and beneath the second surface of the second substrate.

21. The method of claim 17, wherein the bonding of the first surface of the first substrate to the first surface of the second substrate is performed before the thinning of the second substrate.

22. The method of claim 17, wherein the bonding of the first surface of the first substrate to the first surface of the second substrate is performed after the thinning of the second substrate.

23. The method of claim 17, further comprising thinning the second substrate to a thickness of less than 50 microns.

24. A method of making a circuit structure comprising:

forming a first substrate with a first surface having interconnections;

forming a second substrate with a first surface having interconnections, and a second surface, wherein the second surface is opposite said first surface of the second substrate;

bonding the first surface of the first substrate to the first surface of the second substrate;

thinning the second substrate from the second surface;

performing Chemical Mechanical Polishing of the second surface of the second substrate;

depositing a dielectric on the second surface of the second substrate; and

,

forming at least one vertical interconnection between one of the interconnections of the first substrate and one of the interconnections of the second substrate, wherein said at least one interconnection is formed in whole or in part from the first surface of the second substrate, or in whole or in part from the second surface of the second substrate.

25. The method of claim 24, further comprising:

forming a third substrate with a first surface having interconnections; and

bonding the first surface of the third substrate to the second surface of the second substrate.

26. The method of claim 25, further comprising the step of forming a connection between the at least one vertical interconnection and at least one of the interconnections of first surface of the third substrate.

27. The method of claim 24, further comprising forming of interconnections at least one of on, within and beneath the second surface of the second substrate.

28. The method of claim 24, further comprising thinning the second substrate to a thickness of less than 50 microns.

29. A method of making a circuit structure comprising:

forming a first substrate with a first surface having one or more integrated circuits formed thereon;

forming a second substrate with a first surface having one or more integrated circuits formed thereon and a second surface, wherein the second surface is opposite said first surface of the second substrate;

bonding the first surface of the first substrate to the first surface of the second substrate;

thinning the second substrate from the second surface;

performing Chemical Mechanical Polishing of the second surface of the second substrate; and

,

forming at least one vertical interconnection between one of the integrated circuits of the first surface of the first substrate and terminating one of on, within and beneath the second surface of the second substrate, wherein the said at least one vertical interconnection is formed in whole or in part from the first surface of the second substrate, or in whole or in part from the second surface of the second substrate.

30. The method of claim 29, further comprising:

forming a third substrate with a first surface having one or more integrated circuits formed thereon; and

bonding the first surface of the third substrate to the second surface of the second substrate.

31. The method of claim 30, further comprising the step of forming an interconnection between at least one of the one or more integrated circuits of the first surface of the second substrate and at least one of the one or more integrated circuits of first surface of the third substrate.

32. The method of claim 29, further comprising forming of interconnections at least one of on, within and beneath the second surface of the second substrate.

33. The method of claim 30, further comprising forming of interconnections at least one of on, within and beneath the second surface of the third substrate.

34. The method of claim 29, further comprising thinning the second substrate to a thickness of less than 50 microns.

35. A method of making a circuit structure comprising:

forming a first substrate with a first surface having one or more integrated circuits formed thereon and a second surface, wherein the second surface is opposite said first surface of the first substrate;

thinning the first substrate from the second surface;

performing Chemical Mechanical Polishing on the second surface of the first substrate;

forming a second substrate with a first surface having one or more integrated circuits formed thereon and a second surface, wherein the second surface is opposite said first surface of the second substrate;

thinning the second substrate from the second surface;

performing Chemical Mechanical Polishing of the second surface of the second substrate;

bonding the first surface of the second substrate to the second surface of the first substrate; and

forming an interconnection between at least one of the one or more integrated circuits of the first substrate and at least one of the one or more integrated circuits of the second substrate.

36. The method of claim 35, further comprising:

forming a third substrate with a first surface having one or more integrated circuits formed thereon; and

bonding the first surface of the third substrate to one of the first surface of the second substrate and the second surface of the second substrate.

37. The method of claim 36, further comprising the step of forming an interconnection between at least one of the one or more integrated circuits of the first surface of the second substrate and at least one of the one or more integrated circuits of first surface of the third substrate.

38. The method of claim 35, further comprising forming of interconnections at least one of on, within and beneath the second surface of the second substrate.

39. The method of claim 36, further comprising forming of interconnections at least one of on, within and beneath the second surface of the third substrate.

40. The method of claim 35, further comprising depositing a dielectric on the second surface of the first substrate.

41. The method of claim 35, further comprising depositing a dielectric on the second surface of the second substrate.

42. The method of claim 35, further comprising thinning the first substrate to a thickness of less than 50 microns.

43. The method of claim 35, further comprising thinning the second substrate to a thickness of less than 50 microns.

44. A method of making a circuit structure comprising:

forming at least one substrate of a first type with a first surface having one or more integrated circuits formed thereon and a second surface, wherein the second surface is opposite said first surface of the first substrate;

forming at least one substrate of a second type with a first surface having one or more integrated circuits formed thereon and a second surface, wherein the second surface is opposite said first surface of the first substrate, wherein the first surface is bonded to a support substrate with an intervening release layer;

thinning a first substrate of the second type from the second surface and polishing the second surface of the second substrate; and

performing bonding of at least one of;

the first surface of a first substrate of the first type to the second surface of the first substrate of the second type;

the first surface of the first substrate of the first type to the first surface of a second substrate of the first type;

the first surface of the first substrate of the first type to the second surface of a second substrate of the first type;

the second surface of the first substrate of the second type to the second surface of a second substrate of the second type; and

the second surface of the first substrate of the first type to the second surface of a second substrate of the first type;

wherein before performing bonding the second surface of the first substrate of the first type has been thinned and polished.

45. The method of claim 45, comprising:

performing bonding of at least one of;

the first surface of the first substrate of the first type to the first surface of a second substrate of the first type;

the first surface of the first substrate of the first type to the second surface of a second substrate of the first type; and

the second surface of the first substrate of the first type to the second surface of a second substrate of the first type;

wherein before performing bonding the second surface of the second substrate of the first type has been thinned and polished.