Non-volatile memory structure and method of fabrication

• US 20100173464A1
• Filed: 12/10/2009
• Published: 07/08/2010
• Est. Priority Date: 10/14/2004
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Lusky, Eli, Irani, Rustom, Shappir, Assaf
• Granted Patent: US 7,964,459 B2
• Time in Patent Office: Days
• US Class Current: 438/287
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Claims

1. A method for creating a non-volatile memory array, the method comprising:

implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering said substrate;

generating increased-width polysilicon columns from said mask columns;

generating bit lines in said substrate at least between said increased-width polysilicon columns; and

depositing oxide at least between said polysilicon columns.

2. The method according to claim 1 and wherein said generating polysilicon columns comprises:

generating spacers to the sides of said mask columns; and

etching at least said first polysilicon layer between said spacers to generate said increased-width polysilicon columns.

3. The method according to claim 2 and wherein said spacers are one of the following materials:

nitride and oxide.

4. The method according to claim 1 and wherein said generating bit lines comprises implanting said bit lines and performing a rapid thermal anneal.

5. The method according to claim 2 and wherein said etching etches to one of the following layers:

a top layer of said ONO layer, a bottom layer of said ONO layer and said substrate.

6. The method according to claim 2 wherein said etching etches to either one of the following:

a bottom layer of said ONO layer and said substrate and also comprising depositing a protective spacer between said polysilicon columns.

7. The method according to claim 2 and wherein said generating polysilicon columns also comprises removing said mask columns and said spacers after said etching.

8. The method according to claim 2 and wherein said depositing oxide occurs before removing said mask columns and said spacers.

9. The method according to claim 2 and wherein said depositing oxide occurs after removing said mask columns and said spacers.

10. The method according to claim 7 and also comprising planarizing said array to the height of said increased-width polysilicon columns and removing said mask columns and said spacers before said planarizing.

11. The method according to claim 7 and also comprising planarizing said array to the height of said mask columns and removing said mask columns and said spacers after said planarizing.

12. The method according to claim 1 wherein said generating polysilicon columns comprises etching polysilicon between said mask columns and generating polysilicon spacers to the sides of said polysilicon columns.

13. The method according to claim 12 and also comprising:

depositing second polysilicon on top of said planarized array;

etching said second polysilicon into word lines;

removing a portion of said deposited oxide between said increased-width polysilicon columns and said word lines; and

etching said increased-width polysilicon columns between said word lines into gates.

14. The method according to claim 12 and wherein the thickness of said polysilicon columns is at least 20 nm thick.

15. The method according to claim 13 and wherein the thickness of said second polysilicon is at least 20 nm thick.

16. The method according to claim 1 and wherein said non-volatile memory array is a nitride read only memory (NROM) array.