Virtual Platform and Related Simulation Method

• US 20100174519A1
• Filed: 12/23/2009
• Published: 07/08/2010
• Est. Priority Date: 01/08/2009
• Status: Abandoned Application

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Bu, Yong-Hua
• Application Number:
  US12/646,945
• Publication Number:
  US 20100174519A1
• Time in Patent Office: Days
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A platform for simulating a chip includes a component module, a configuration module and a top module. The component module is utilized for storing a plurality of component models and information related to the plurality of component models. The configuration module is utilized for generating a configuration result according to the component model needed by the chip. The top module is coupled to the component module and the configuration module, for reading information related to the component model from the component module according to the configuration result, so as to simulate the chip.

Claims

1. A platform for simulating a chip comprising:

a component module, for storing a plurality of component models and information related to the plurality of component models;

a configuration module, for generating a configuration result according to a component model needed by the chip; and

a top module, coupled to the component module and the configuration module, for reading information related to the component model from the component module according to the configuration result so as to simulate the chip.

2. The platform of claim 1, wherein the information related to the plurality of component models comprises a name and a connecting method of the plurality of component models.

3. The platform of claim 2, wherein the plurality of component models are built with classes of C++.

4. The platform of claim 2, wherein the component module is an extendable module, and a new component model of the component module is compiled as a dynamic library file and is stored in a specified directory.

5. The platform of claim 4, wherein, when simulating the system-on-chip, the top module reads the dynamic library file in the specified directory, to obtain the new component model, and generates an instance of the new component model by dynamically loading.

6. The platform of claim 5, wherein the top module generates the instance of the new component model by an extending function.

7. The platform of claim 1, wherein the component model is a processor.

8. The platform of claim 1, wherein the component model is a timer.

9. A method for simulating a chip comprising:

establishing a plurality of component models and information related to the plurality of component models;

generating a configuration result according to a component model needed by the chip; and

reading information related to the component models from the plurality of component models according to the configuration result, so as to simulate the chip.

10. The method of claim 9, wherein the information related to the plurality of component models comprises a name and a connecting method of the plurality of component models.

11. The method of claim 10, wherein the plurality of component models are built with classes of C++.

12. The method of claim 10, wherein the plurality of component models are extendable, and a new component model is compiled as a dynamic library file and is stored in a specified directory.

13. The method of claim 12, wherein, when simulating the chip, the method is related to read the dynamic library file in the specified directory, to obtain the new component model, and is related to generate an instance of the new component model by dynamically loading.

14. The method of claim 13, wherein generating the instance of the new component model by the dynamic loading method is related to generate the instance of the new component model by an extending function.

15. The method of claim 9, wherein the component model is a processor.

16. The method of claim 9, wherein the component model is a timer.