MEMORY SYSTEM CONTROLLER

• US 20100174851A1
• Filed: 01/08/2009
• Published: 07/08/2010
• Est. Priority Date: 01/08/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Leibowitz, Robert N., Feeley, Peter
• Granted Patent: US 8,412,880 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host interface communicatively coupled to a system controller. The system controller has a number of memory interfaces, and is configured for controlling a plurality of intelligent storage nodes communicatively coupled to the number of memory interfaces. The system controller includes logic configured to map between physical and logical memory addresses, and logic configured to manage wear level across the plurality of intelligent storage nodes.

Claims

1. A memory system controller, comprising:

a host interface; and

a system controller communicatively coupled to the host interface, and having a number of memory interfaces,

wherein the system controller is configured for controlling a plurality of intelligent NAND storage nodes (INSNs) communicatively coupled to the number of memory interfaces, the system controller including logic configured to map between physical and logical memory addresses, and logic configured to manage wear level across the plurality of INSNs.

2. The memory system controller of claim 1, wherein the memory interfaces are synchronous memory interfaces.

3. The memory system controller of claim 2, wherein a first portion of the INSNs are communicatively coupled in parallel to one of the number of synchronous memory interfaces.

4. The memory system controller of claim 3, wherein a second portion of the INSNs are communicatively coupled in parallel to a different one of the number of synchronous memory interfaces.

5. The memory system controller of claim 1, wherein the memory interfaces are serial memory interfaces.

6. The memory system controller of claim 5, wherein the system controller is configured to generate physical page memory access requests without logical block information.

7. The memory system controller of claim 5, wherein each of the number of serial memory interfaces are configured to communicate with at least two INSNs communicatively coupled thereto.

8. The memory system controller of claim 5, wherein the system controller includes logic configured to manage wear level across all of the INSNs.

9. The memory system controller of claim 5, wherein the INSNs each have a number of memory devices.

10. The memory system controller of claim 9, wherein the logic configured to manage wear level across the number of INSNs includes logic to manage wear leveling across the number of memory devices of a particular INSN.

11. The memory system controller of claim 9, wherein the logic configured to manage wear level across the number of INSNs includes logic configured to manage wear leveling across the number of memory devices of a plurality of INSNs.

12. The memory system controller of claim 11, wherein the logic configured to manage wear level across the number of INSNs includes logic configured to manage wear leveling across all memory devices of all INSNs.

13. A memory system, comprising:

a system controller and host interface (SCHI), including;

a host interface, and

a memory system controller communicatively coupled to the host interface, and having at least two serial memory interfaces; and

a plurality of storage nodes communicatively coupled to the at least two serial memory interfaces,

wherein the memory system controller is configured for controlling the plurality of storage nodes including providing centralized physical to logical address translation for the plurality of storage nodes, and managing wear leveling across the plurality of storage nodes.

14. The memory system of claim 13, wherein the plurality of storage nodes are intelligent NAND storage nodes (INSNs).

15. The memory system of claim 13, wherein the plurality of storage nodes include a number of memory devices.

16. The memory system of claim 15, wherein the plurality of storage nodes each include a node memory controller communicatively coupled to a number of memory devices.

17. The memory system of claim 16, wherein the number of memory devices are NAND flash memory devices.

18. The memory system of claim 17, wherein each node memory controller is communicatively coupled to the number of NAND flash memory devices by an open NAND flash interface (ONFi).

19. The memory system of claim 18, wherein the plurality of storage nodes are each configured in a multichip package.

20. The memory system of claim 19, wherein the multichip package has less than 20 pins.

21. The memory system of claim 20, wherein the multichip package has no more than three pins for data and control signals.

22. The memory system of claim 15, wherein the plurality of storage nodes are solid state drives.

23. A memory system, comprising:

a plurality of intelligent NAND storage nodes (INSNs); and

a memory system controller communicatively coupled to a first portion of the plurality of INSNs through a first serial interface, and communicatively coupled to a second portion of the plurality of INSNs through a second serial interface,

wherein the memory system controller is configured to map between logical addresses utilized by a host system and physical addresses utilized by the plurality of INSNs, and the memory system controller is configured to manage wear leveling across the plurality of INSNs.

24. The memory system of claim 23, wherein the first portion of the plurality of INSNs includes multiple INSNs.

25. The memory system of claim 24, wherein the second portion of the plurality of INSNs includes multiple INSNs.

26. The memory system of claim 24, wherein the first and second serial interfaces are a serial communication bus, and the first portion of the plurality of INSNs are arranged in a daisy chain to the first serial communication bus, and the second portion of the plurality of INSNs are arranged in a daisy chain to the second serial communication bus.

27. The memory system of claim 26, wherein each of the INSNs include a bus management module.

28. The memory system of claim 27, wherein each bus management module is communicatively coupled to the node memory controller, and configured to control a serial communication bus for transmitting data to the memory system controller.

29. The memory system of claim 27, wherein the plurality of INSNs each include a number of NAND flash memory devices, and a node controller communicatively coupled between the NAND flash memory devices thereon and the node controller.

30. The memory system of claim 29, wherein each node controller is configured to control NAND flash memory device access and manage NAND flash memory device defects.

31. The memory system of claim 29, wherein each node controller is configured to detect and correct errors in data stored in the NAND flash memory devices.

32. A method of operating a memory system, comprising:

establishing communications between a plurality of storage nodes and a memory system controller using a number of serial communication interfaces, each of the plurality of storage nodes having a node controller communicatively coupled between a particular serial communication interface and a number of memory devices;

managing wear leveling among the plurality of storage nodes at the memory system controller; and

translating between logical addresses and physical addresses for the plurality of storage nodes at the memory system controller.

33. The method of claim 32, including managing wear leveling among the number of memory devices of a particular storage node at the memory system controller.

34. The method of claim 33, including managing error correction among the number of memory devices of a particular storage node at the node controller associated with the particular storage node.

35. The method of claim 34, including managing wear leveling among the number of memory devices of multiple storage nodes at the memory system controller.

36. The method of claim 35, wherein managing wear leveling among the number of memory devices of multiple storage nodes includes detecting differences in wear between number of memory devices.

37. The method of claim 35, wherein managing wear leveling among the number of memory devices of multiple storage nodes includes detecting wear above a limit in an individual memory device.

38. The method of claim 37, wherein the limit is a preset fixed limit.

39. The method of claim 37, wherein the limit is a dynamic limit.

40. A method for operating a memory system, comprising:

receiving a write command and associated data corresponding to a range of logical addresses from a host system;

determining at a memory system controller, based on wear leveling among a number of storage nodes, a particular storage node of the number of storage nodes in which to store the associated data;

mapping the range of logical addresses to physical addresses of the particular storage node; and

transmitting the data serially through a daisy chain of storage nodes to the particular storage node.

41. The method of claim 40, wherein the number of storage nodes are intelligent NAND storage nodes (INSNs), and the method includes communicating physical page access requests by the memory system controller to the INSNs without referencing logical blocks.

42. The method of claim 41, including translating disk drive protocols into raw NAND commands on the memory system controller before transmitting the data serially through a daisy chain of storage nodes.