Regulating Power Consumption

• US 20100174923A1
• Filed: 01/07/2009
• Published: 07/08/2010
• Est. Priority Date: 01/07/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines SA (International Business Machines Corporation)
• Inventors: McGowan, Dilton Monroe II, Houlihan, John Richard
• Granted Patent: US 8,122,269 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods, systems, and design structures for providing power-regulated multi-core processing. The method includes determining a configuration of processing cores for optimal power consumption. The configuration of processing cores for optimal power consumption comprises a managing core and zero or more active processing cores wherein the active processing cores are selected from one or more available processing cores operatively coupled to the managing core. The managing core receives processing requests and processes them by dynamically retaining or distributing power to the configuration of processing cores. The managing core presents an appearance of a single core to an electronic system comprising the processing cores.

Claims

1. A method for providing power-regulated multi-core processing comprising:

determining a configuration of processing cores for optimal power consumption, the configuration of processing cores comprising a managing core and zero or more active processing cores, the active processing cores selected from one or more available processing cores operatively coupled to the managing core;

receiving one or more processing requests at the managing core;

the managing core dynamically distributing power to the configuration of processing cores and dynamically retaining or distributing processing requests to the configuration of processing cores, the managing core presenting an appearance of a single core to an electronic system.

2. The method of claim 1 wherein determining the configuration of processing cores comprises comparing, in the managing core, operational conditions with at least one of a plurality of threshold values stored in a memory.

3. The method of claim 2, wherein the managing core is configured to be operatively coupled to either a continuous power source or a battery power source and the plurality of threshold values stored in the memory comprise a first set of threshold values for continuous power and a second set of threshold values for battery power, and wherein determining the configuration of processing cores for optimal power consumption comprises:

determining whether the managing core is operatively coupled to the continuous power source or the battery power source;

upon determining that the managing core is operatively coupled to the continuous power source, comparing the operational conditions with the first set of threshold values to determine a first configuration of processing cores; and

upon determining that the managing core is operatively coupled to the battery power source, comparing the operational conditions with the second set of threshold values to determine a second configuration of processing cores.

4. The method of claim 1 wherein determining the configuration of processing cores comprises:

selecting a core startup latency value from a set of predetermined core startup latency values stored in memory in dependence upon operating conditions, wherein the predetermined core startup latency values are configured to prevent vacillation of the actual configuration;

determining whether a processing load has exceeded a current aggregate processing capacity for a duration of time not less than the selected core startup latency value; and

incrementing the number of active processing cores in the configuration of processing cores for optimal power consumption if the processing load has exceeded the current aggregate processing capacity for the duration of time not less than the selected core startup latency value.

5. The method of claim 4, wherein selecting a core startup latency value from a set of predetermined core startup latency values stored in memory in dependence upon operating conditions comprises selecting a core startup latency value in dependence upon at least one of an average processing load and remaining power of a battery power source.

6. The method of claim 1 wherein determining the configuration of processing cores comprises:

selecting a core quiescence time value from a set of predetermined core quiescence time values stored in memory in dependence upon operating conditions, wherein the predetermined core quiescence time values are configured to prevent vacillation of the actual configuration;

determining whether a processing load has remained below a processing capacity corresponding to a lower power configuration of processing cores for a duration of time not less than the selected core quiescence time value; and

decrementing the number of active processing cores in the configuration of processing cores so that the configuration of processing cores corresponds to the lower power configuration of processing cores if the processing load has remained below the processing capacity corresponding to the lower power configuration of processing cores for the duration of time not less than the selected core quiescence time value.

7. The method of claim 6 further comprising determining the core quiescence time value in dependence upon at least one of an average processing load and remaining power of a battery power source.

8. The method of claim 1 wherein the configuration of processing cores includes the managing core, the method further comprising receiving a processing request at the managing core.

9. The method of claim 8 wherein, if a current processing load is less than a processing capability of the managing core, the configuration of processing cores comprises only the managing core.

10. The method core of claim 8, wherein, the processing request is configured for execution by a single core.

11. A managing core configured to be operatively coupled to one or more available processing cores and a power source, the managing core comprising:

a memory for storing threshold values;

an operational conditions monitoring circuit configured to determine operational conditions;

an optimizing circuit configured to compare the operational conditions with the threshold values to determine an configuration of processing cores including the managing core and zero or more active processing cores selected from one or more available processing cores;

load distributor circuits configured to distribute power to the one or more available processing cores so that an actual configuration of processing cores corresponds to the configuration of processing cores;

processor circuits configured to process processing requests assigned to the managing core;

input circuits configured to receive a processing request, the processing request configured for execution by a single core; and

programmed logic circuits configured to assign the processing request to one of the managing core and one of the one or more active processing cores.

12. The managing core of claim 11 wherein the managing core and the one or more available processing cores comprise embedded cores.

13. The managing core of claim 12, further comprising an interface including one or more input lines and an input circuit configured to store threshold values in the memory responsive to signals received at the one or more input lines.

14. The managing core of claim 12, wherein:

the managing core is configured to be operatively coupled to both a continuous power source and a battery power source;

the memory for storing threshold values stores a first set of threshold values for continuous power and a second set of threshold values for battery power;

the operational conditions monitoring circuit is configured to detect that the managing core is operatively coupled to the continuous power source; and

the optimizing circuit is configured to;

compare the operational conditions with the first set of threshold values to determine a first configuration of processing cores for optimal power consumption if the detection circuit detects that the managing core is operatively coupled to the continuous power source; and

compare the operational conditions with the second set of threshold values to determine a second configuration of processing cores if the detection circuit does not detect that the managing core is operatively coupled to the continuous power source.

15. The managing core of claim 11, and wherein the optimizing circuit is configured such that the configuration of processing cores comprises only the managing core if a current processing load is less than the processing capability of the managing core.

16. A system comprising:

a managing core operatively coupled to a power source and one or more available processing cores configured to execute processing requests, the managing core comprising;

a memory for storing threshold values;

an operational conditions monitoring circuit configured to determine operational conditions;

an optimizing circuit configured to compare the operational conditions with the threshold values to determine a configuration of processing cores for optimal power consumption including the managing core and zero or more active processing cores, the active processing cores selected from the one or more available processing cores;

load distributor circuits configured to distribute power to the one or more available processing cores so that an actual configuration of processing cores corresponds to the configuration of processing cores for optimal power consumption;

processor circuits configured to process processing requests assigned to the managing core;

input circuits configured to receive a processing request, the processing request configured for execution by a single core; and

programmed logic circuits configured to assign the processing request to one of the processing cores in the actual configuration of processing cores.

17. The system of claim 16, wherein the system is an integrated circuit.

18. A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:

a managing core configured to be operatively coupled to one or more available processing cores and a power source, the managing core comprising;

a memory for storing threshold values;

an operational conditions monitoring circuit configured to determine operational conditions;

an optimizing circuit configured to compare the operational conditions with the threshold values to determine a configuration of processing cores for optimal power consumption including the managing core and zero or more active processing cores, the active processing cores selected from one or more available processing cores;

load distributor circuits configured to distribute power to the one or more available processing cores so that an actual configuration of processing cores corresponds to the configuration of processing cores for optimal power consumption;

processor circuits configured to process processing requests assigned to the managing core;

input circuits configured to receive a processing request, the processing request configured for execution by a single core; and

programmed logic circuits configured to assign the processing request to one of the processing cores in the actual configuration of processing cores.

19. The design structure of claim 18, wherein the design structure comprises a netlist which describes the managing core.

20. The design structure of claim 18, wherein the design structure resides on the machine readable storage medium as a data format used for the exchange of layout data of integrated circuits.