POWER MOSFET AND METHOD OF FABRICATING THE SAME

• US 20100176444A1
• Filed: 02/19/2009
• Published: 07/15/2010
• Est. Priority Date: 01/09/2009
• Status: Abandoned Application

• Current Assignee: Niko Semiconductor Co., Ltd
• Original Assignee: Niko Semiconductor Co., Ltd
• Inventors: Hsu, Hsiu-Wen, Tu, Kou-Way
• Application Number:
  US12/389,360
• Publication Number:
  US 20100176444A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET including a substrate of first conductivity type, an epitaxial layer of first conductivity type on the substrate, a body layer of second conductivity type in the epitaxial layer, a first insulating layer, a second insulating layer, a first conductive layer and two source regions of first conductivity type is provided. The body layer has a first trench therein. The epitaxial layer has a second trench therein. The second trench is below the first trench, and the width of the second trench is much smaller than that of the first trench. The first insulating layer is at least in the second trench. The first conductive layer is in the first trench. The second insulating layer is at least between the sidewall of the first trench and the first conductive layer. The source regions are disposed in the body layer beside the first trench respectively.

Claims

1. A power MOSFET, comprising:

a substrate of a first conductivity type;

an epitaxial layer of the first conductivity type, disposed on the substrate;

a body layer of a second conductivity type, disposed in the epitaxial layer, wherein the body layer has a first trench therein, the epitaxial layer has a second trench therein, the second trench is disposed below the first trench, and a width of the second trench is much smaller than a width of the first trench;

a first insulating layer, at least disposed in the second trench;

a first conductive layer, disposed in the first trench;

a second insulating layer, at least disposed between a sidewall of the first trench and the first conductive layer; and

two source regions of the first conductivity type, disposed in the body layer beside the first trench respectively.

2. The power MOSFET of claim 1, further comprising two heavily doped regions of the first conductivity type, disposed in the epitaxial layer below the first trench and beside the second trench.

3. The power MOSFET of claim 1, wherein an included angle between a sidewall of the second trench and a bottom of the first trench is greater than or equal to 90 degree.

4. The power MOSFET of claim 1, wherein the width of the first trench is 2-3 times the width of the second trench.

5. The power MOSFET of claim 1, wherein a depth of the first trench is greater than 0.8 um and a depth of the second trench is greater than 0.15 um.

6. The power MOSFET of claim 1, wherein a portion of the second insulating layer is disposed between the first conductive layer and the epitaxial layer.

7. The power MOSFET of claim 1, wherein the first trench extends to the epitaxial layer below the body layer.

8. A method of fabricating a power MOSFET, comprising:

forming an epitaxial layer of a first conductivity type on the substrate of the first conductivity type;

forming a first trench in the epitaxial layer;

forming a second trench below the first trench, wherein a width of the second trench is smaller than a width of the first trench;

forming a first insulating layer to at least fill up the second trench;

forming a second insulating layer at least on a sidewall of the first trench;

forming a first conductive layer in the first trench;

forming a body layer of a second conductivity type in the epitaxial layer around the first trench; and

forming two source regions of the first conductivity type in the body layer beside the first trench.

9. The method of claim 8, further comprising forming a heavily doped region of the first conductivity type below the first trench after the step of forming the first trench and before the step of forming the second trench.

10. The method of claim 9, wherein the second trench penetrates the heavily doped region.

11. The method of claim 8, further comprising forming two heavily doped regions of the first conductivity type beside the second trench after the step of forming the second trench and before the step of forming the second insulating layer.

12. The method of claim 8, wherein an included angle between a sidewall of the second trench and a bottom of the first trench is greater than or equal to 90 degree.

13. The method of claim 8, wherein the step of forming the second trench comprises:

forming a spacer on the sidewall of the first trench; and

removing a portion of the epitaxial layer by using the spacer as a mask, so as to form the second trench below the first trench.

14. The method of claim 13, wherein the step of forming the spacer comprises:

forming a spacer material layer conformally on the substrate; and

performing an anisotropic etching to remove a portion of the spacer material layer.

15. The method of claim 13, wherein the step of forming the first insulating layer comprises:

forming an insulating material layer on the substrate to fill up the first trench and the second trench;

performing an etching back process to remove a portion of the insulating material layer, so as to form the first insulating layer; and

removing the spacer.

16. The method of claim 13, wherein the step of forming the first insulating layer comprise:

forming an insulating material layer on the substrate to fill up the first trench and the second trench; and

performing an etching back process to remove the spacer and a portion of the insulating material layer, so as to form the first insulating layer.

17. The method of claim 13, wherein the step of forming the first insulating layer comprises:

removing the spacer;

forming an insulating material layer on the substrate to fill up the first trench and the second trench; and

performing an etching back process to remove a portion of the insulating material layer, so as to form the first insulating layer.

18. The method of claim 8, wherein the first insulating layer and the second insulating layer are formed simultaneously by performing a thermal oxidation process.

19. The method of claim 8, wherein the width of the first trench is 2-3 times the width of the second trench.

20. The method of claim 8, wherein a depth of the first trench is greater than 0.8 um and a depth of the second trench is greater than 0.15 um.