ASSEMBLY OF NANOSCALED FIELD EFFECT TRANSISTORS

• US 20100176459A1
• Filed: 09/19/2007
• Published: 07/15/2010
• Est. Priority Date: 09/19/2006
• Status: Active Grant

• Current Assignee: QuNano AB
• Original Assignee: QuNano AB
• Inventors: Bryllert, Tomas, Samuelson, Lars, Lind, Erik, Ohlsson, Jonas, Löwgren, Truls, Wernersson, Lars-Erik, Thelander, Claes
• Granted Patent: US 8,063,450 B2
• Time in Patent Office: Days
• US Class Current: 257/392
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.

Claims

1. A semiconductor device comprising at least two vertical nanowire wrap insulating gate field effect transistors (101, 102), characterized in that each transistor comprises a massive nanowire (105) which comprises the channel of the transistor, and by that one of the transistors differ in the threshold voltage from the other transistor.

2. The semiconductor device according to claim 1, wherein the nanowire transistors are grouped into at least two individually addressable sets that each consist of nanowires with the same threshold voltage.

3. The semiconductor device according to claim 2, characterized by a first set (405) of transistors comprising nanowires each of a first diameter giving a first threshold voltage, and a second set (406) of transistor comprising nanowires each of a second diameter giving a second threshold voltage.

4. The semiconductor device according to claim 3, wherein the first set of transistors are of enhancement type and the second set of transistors are of depletion type and the diameter of the nanowires in the first set (405) is smaller than the diameter of the nanowires in the second set (406).

5. The semiconductor device according to claim 4, wherein the diameter of the nanowires in the first set of transistors is below 20 nm.

6. The semiconductor device according to claim 2, characterized by a first set of transistors comprising nanowires each with a first doping level giving a first threshold voltage, and a second set of transistor comprising nanowires each with a second doping level giving a second threshold voltage.

7. The semiconductor device according to claim 6, wherein the first set of transistors are of enhancement type and the second set of transistors are of depletion type and the doping level of the nanowires in the first set is lower than the doping level of the nanowires in the second set.

8. The semiconductor device according to claim 7, wherein the doping levels are in the interval 10¹⁶-10¹⁸ cm⁻

3.

9. The semiconductor device according to claim 2, wherein each of the transistors comprises a gate stack comprising a gate contact (160) enclosing a portion of the nanowire (105), and a dielectric layer (170) between the gate contact (160) and the nanowire (105), characterized by a first set of transistors comprising nanowires each with a first gate stack exhibiting a first work function giving a first threshold voltage, and a second set of transistor comprising nanowires each with a second gate stack exhibiting a second work function giving a second threshold voltage.

10. The semiconductor device according to claim 9, wherein the first set of transistors are of enhancement type and the second set of transistors are of depletion type and the first gate stacks have a larger work function than the second gate stacks.

11. The semiconductor device according to claim 10, wherein the first gate stack comprises a gate contact of a first metal or metal combination and the second gate stack comprises a gate contact of a second metal or metal combination, and wherein the first metal or metal combination has a larger work function than the second metal or metal combination.

12. The semiconductor device according to claim 10, wherein the first gate stack comprises a doped layer with a first doping level giving a first work function and the second gate stack comprises a doped layer with a second doping layer different from the first doping layer giving a second work function.

13. The semiconductor device according to claim 2, wherein the transistors comprises a gate contact (160) enclosing a portion of the nanowire (105), the enclosed portion defining a gate region (107), characterized by a first set of transistors comprising nanowires (105) each with a first heterostructure in the gate region (107) giving a first threshold voltage, and a second set of transistor comprising nanowires each with a second heterostructure or no heterostructure in the gate region (107) giving a second threshold voltage.

14. The semiconductor device according to claim 13, wherein the first set of transistors are of enhancement type and the second set of transistors are of depletion type and the heterostructure in the nanowires of the first set of transistors forms a larger barrier than the heterostructure in the nanowires of the second set of transistors.

15. The semiconductor device according to claim 2, wherein the nanowires (105) are at least partly enclosed by a doped shell layer (1010) and a first set of transistors each provided with a first shell layer (107) providing a first carrier concentration to the enclosed nanowire giving a first threshold voltage, and a second set of transistor each provided with a second shell layer (107) providing a second carrier concentration, different from the first carrier concentration, to the enclosed nanowire giving a second threshold voltage.

16. The semiconductor device according to claim 15, wherein the first and second doped shell layer differ in thickness.

17. The semiconductor device according to claim 15 or 16, wherein the first and second doped shell layer differ in doping level.

18. The semiconductor device according to claim 2, wherein a first set of transistors each arranged according to a structure resulting in a first strain in the nanowire giving a first threshold voltage, and a second set of transistor each arranged according to a structure resulting in a second strain in the nanowire giving a second threshold voltage.

19. The semiconductor device according to claim 18, wherein the transistor in the first set has a first core/shell-structure and the transistors in the second set has a different core/shell structure.

20. The semiconductor device according to claim 2, wherein each of the transistors comprises a gate stack comprising a gate contact (160) enclosing a portion of the nanowire (105), and a dielectric layer (170) between the gate contact (160) and the nanowire (105), characterized by a first set of transistors comprising a first gate stack with a first dielectric layer, and a second set of transistor comprising a second gate stack with a second dielectric layer, wherein the first and second dielectric layer differ in thickness or in permittivity.

21. The semiconductor device according to claim 20, wherein the first set of transistors are of enhancement type and the second set of transistors are of depletion type and the first dielectric layer is thinner or has a higher permittivity than the second dielectric layer.

22. The semiconductor device according to claim 2, characterized by a first set of transistors comprising nanowires of a first material and a second set of transistor comprising nanowires of a second material wherein the materials differ in bandgap.

23. The semiconductor device according to claim 22, wherein the first set of transistors are of enhancement type and the second set of transistors are of depletion type and the first material has a larger bandgap than the second material.

24. The semiconductor device according to any of the above claims, wherein the transistors with different threshold voltages are formed in the same nanowire.

25. The semiconductor device according to any of claims 1-23, characterized by that the transistors with different threshold voltages are formed during one growth run.

26. The semiconductor device according to any of the above claims, wherein the transistors are of both n-type and p-type.

27. The semiconductor device according to any of the claims 1-25, wherein the transistors are of both n-type and p-type.

28. A method of fabricating a semiconductor device comprising a plurality of nanowires, characterized by the steps of:

growing in a first growth run nanowires with first characteristics at at least one first confined area of a substrate, forming a first set of nanowires;

growing in a second growth run nanowires with second characteristics at at least one second confined area of a substrate, forming a second set of nanowires; and

contacting the first and second set of nanowires so that the sets are individually addressable.

29. The method according to claim 28, wherein the sets of nanowires are characterized by a first and second threshold value.

30. The method according to claim 29, comprising the steps of:

depositing catalytic particles of a first size in at least one first confined area of a substrate;

depositing catalytic particles of a second size in at least one second confined area of the substrate;

growing simultaneously nanowires from both first and second catalytic particle sizes, thereby forming a first set of nanowires with a first diameter and a second set of nanowires with a second diameter, relating respectively to a first and second threshold value; and

contacting the first and second set of nanowires so that the sets are individually addressable.

31. The method according to claim 29, comprising the steps of:

providing a growth mask with apertures of a first diameter in at least one first confined area of a substrate;

providing a growth mask with apertures of a second diameter in at least one second confined area of the substrate;

growing simultaneously nanowires from apertures of first and second diameters, thereby forming a first set of nanowires with a first diameter and a second set of nanowires with a second diameter, relating respectively to a first and second threshold value; and

contacting the first and second set of nanowires so that the sets are individually addressable.