GNSS SUPERBAND ASIC WITH SIMULTANEOUS MULTI-FREQUENCY DOWN CONVERSION

• US 20100176991A1
• Filed: 12/10/2009
• Published: 07/15/2010
• Est. Priority Date: 12/11/2008
• Status: Active Grant

• Current Assignee: Hemisphere GNSS(USA) Incorporated
• Original Assignee: Hemisphere GNSS(USA) Incorporated
• Inventors: Webber, Mark R., Badke, Bradley P., Miller, Steven R., Feller, Walter J.
• Granted Patent: US 8,217,833 B2
• Time in Patent Office: Days
• US Class Current: 342/357.620
• CPC Class Codes: G01S 19/32 Multimode operation in a single same satellite system, e.g. GPS L1/L2
• CPC Class Codes: G01S 19/33 Multimode operation in different systems which transmit time stamped messages, e.g. GPS/GLONASS
• CPC Class Codes: G01S 19/36 relating to the receiver frond end

Abstract

A multi-frequency down converter includes first and second signal paths. A common local oscillator/synthesizer drives both of the signal paths. Exemplary applications include GNSS systems operating across superbands. The down converter is adapted for use in a GNSS receiver system.

Claims

1. An integrated circuit (IC) for simultaneously down converting global navigation satellite system (GNSS) signals in first and second signal frequency bands, which circuit comprises:

first and second signal paths receiving GNSS signals corresponding to the first and second signal frequency bands respectively;

a common local oscillator/synthesizer (LO/Synth) connected to and driving each of said signal paths;

the LO/Synth including a common programmable divider providing a sample clock signal to each of said signal paths and adapted for simultaneously down converting said signals to a lower intermediate frequency (IF); and

first and second analog-to-digital converters (ADCs) each connected to said common programmable divider, each said ADC receiving a down-converted signal as an input and providing a digital signal as an output.

2. The IC according to claim 1 wherein each said signal frequency band comprises a superband of frequencies associated with multiple GNSSs.

3. The IC according to claim 2, which includes:

each said signal path being adapted for connection to and receiving input from a multiplexer with multiple outputs and located externally to said IC;

first and second low-noise amplifiers (LNAs) in said first and second signal paths respectively and each electrically connected to a respective multiplexer output;

said first and second signal paths being adapted for connection to first and second band pass filters (BPFs) located externally to said IC with said first and second BPFs being adapted for connection to said first and second LNAs respectively; and

first and second mixers electrically connected to said LO/Synth in said first and second signal paths respectively and adapted for connection to said first and second BPFs respectively.

4. The IC according to claim 3 wherein the noise bandwidth of the system is set by the BPF in the first IF.

5. The IC according to claim 4 wherein:

the ADC sample clock supports IF sub-sampling of the analog IF signal simultaneously from both ADCs; and

said ADC sample clock is generated by dividing the down converter LO/Synth output by an integer.

6. The IC according to claim 2 wherein the GNSSs are chosen from among the group comprising:

SBAS, GPS, GLONASS and Galileo.

7. The IC according to claim 5, which includes:

a serial peripheral programming interface (SPI) adapted for connection to a device located externally to said IC and adapted for controlling said SPI; and

said frequency dividers in the IC being externally programmable via the SPI.

8. The IC according to claim 1 wherein:

each RF channel has only one IF.

9. The IC according to claim 7, which is adapted for connection to an external power switching device connected to said SPI and adapted for deactivating portions of said circuit and thereby reducing power consumption.

10. The IC according to claim 9, which is adapted for connection to external matching components connected to the RF input, said external matching components being adapted for matching signals to respective super bands.

11. The IC according to claim 10, which includes:

said first and second BPFs comprising first stage BPFs; and

a first second stage BPF and a second second stage BPF in said first and second signal paths respectively and adapted for electrical connection to said first and second mixers respectively.

12. The IC according to claim 3 wherein said BPFs comprise surface acoustic wave band pass filters (SAW BPFs).

13. The IC according to claim 12, which includes:

first and second variable gain amplifiers (VGAs) in said first and second signal paths respectively and electrically connected to said second stage BPFs; and

said first and second ADCs being electrically connected to said first and second VGAs respectively.

14. The IC according to claim 1 wherein the signals in each said RF signal path are differential.

15. The IC according to claim 13, wherein:

said LO/Synth, said SPI, said mixers, said VGAs and said ADCs are collectively contained in an integrated circuit (IC);

said BPFs are located externally to said IC; and

said IC is adapted for electrical connection with said external BPFs.

16. The IC according to claim 1, which includes:

channel to channel isolation means for preventing interference in one channel from interfering with operation of the other channel.

17. The IC according to claim 15, which includes:

said LO/Synth being adapted for electrical connection to a passive loop filter located externally to the IC.

18. The IC according to claim 15, which includes:

an ADC sample clock input to said IC enabling multiple circuits to use a shared sample clock to sample multiple GNSS signals.

19. The IC according to claim 15, which includes:

said LO/Synth including a programmable divide by integer R component; and

said LO/Synth being adapted for electrical connection to an external temperature controlled crystal oscillator (TCXO) connected to said programmable divide by integer R component and adapted for providing a reference signal.

20. The IC according to claim 1, which includes:

an ADC sample clock supporting IF subsampling of both analog IFs.

21. The IC according to claim 20 wherein an ADC sample clock is generated by dividing a down-converter synthesizer output frequency by an integer.

22. The IC according to claim 1, which includes:

said IC being adapted for connection to at least one additional IC adapted for converting multiple pairs of GNSS signals in two super bands; and

said ICs being adapted for connection to a common sample clock for synchronizing the ADC sampling clocks for all signals being clown converted.

23. The IC according to claim 22 wherein said sample clock signal is generated by dividing the LO/Synth output by an integer.

24. The IC according to claim 1, which is adapted for connection to a multiplexer adapted for receiving GNSS signals as input and providing output consisting of at least said first and second signal bands with first and second center frequencies respectively.

25. The IC according to claim 1, which includes:

a serial programming interface (SPI) connected to said signal paths and adapted for connection to an external device for externally controlling the circuit.

26. The IC according to claim 1, which includes:

said LO/Synth being programmable for tuning said circuit to multiple GNSS superbands; and

said LO/Synth includes a frequency divider and is adapted for providing an ADC sample clock output.

27. The IC according to claim 20 wherein:

the ADC outputs are configurable to be either four-bit linear output format or two-bit Lloyd-Max output format.

28. The IC according to claim 1, which includes:

differential IF signal paths.

29. The IC according to claim 1, which includes:

RF and IF signal paths with sufficient bandwidth to down convert all or portions of upper and lower super bands allowing simultaneous reception of multiple GNSSs, including GPS L1 and GLONASS L1 in signal path 1 and GPS L2 and GLONASS L2 in signal path 2.

30. A GNSS receiver system for multiple frequencies, which system includes:

an integrated circuit (IC) for simultaneously down converting GNSS signals in first and second signal frequency bands;

first and second signal paths receiving GNSS signals corresponding to the first and second signal frequency bands respectively;

a common LO/Synth in said IC and connected to and driving each of said signal paths;

the LO/Synth including a common programmable divider providing a sample clock signal to each of said signal paths and adapted for simultaneously down converting said signals to a lower IF;

first and second ADCs in said IC and each connected to said common programmable divider, each said ADC receiving a down-converted signal as an input and providing a digital signal as an output;

said IC adapted for connections with elements external to said IC;

first and second LNAs located in said IC within said first and second signal paths respectively and each electrically connected to a respective multiplexer output;

first and second first stage BPFs connected to said first and second signal paths respectively;

first and second second stage BPFs connected to said first and second signal paths respectively;

said first stage BPFs being connected to said first and second LNAs respectively;

a serial peripheral programming interface (SPI) adapted for connection to a device located externally to said IC and adapted for controlling said SPI; and

said frequency dividers in the IC being externally programmable via the SPI.

31. The system according to claim 30, which includes:

an active antenna;

multiple downconverter ICs receiving input from an active antenna and providing output to an application-specific integrated circuit ASIC;

a common clock connected to said ICs;

said ICs providing input to a correlator application-specific integrated circuit (ASIC); and

and

a GNSS solution processor connected to and receiving output from said correlator ASIC.

32. The system according to claim 30, which is configured for a GNSS signal pair chosen from among the GNSS signal pairs including:

GPS-L1/GPS-L2 with a first first stage BPF frequency of 1575.42 MHz, a second first stage BPF frequency of 1227.6 MHz, a first second stage BPF frequency of 173.91 MHz, a second second stage BPF frequency of 173.91 MHz and an LO/Synth output frequency of 1401.5 MHz;

GPS-L1/GPS-L5 with a first first stage BPF frequency of 1575.42 MHz, a second first stage BPF frequency of 1176.45 MHz, a first second stage BPF frequency of 200 MHz, a second second stage BPF frequency of 200 MHz and an LO/Synth output frequency of 1375.9 MHz; and

GPS-L1/GLONASS-L1 with a first first stage BPF frequency of 1602 MHz, a second first stage BPF frequency of 1575.42 MHz, a first second stage BPF frequency of 200 MHz, a second second stage BPF frequency of 173.91 MHz and an LO/Synth output frequency of 1375.9 MHz.

33. A GNSS receiver system for multiple frequencies, which system includes:

an integrated circuit (IC) for simultaneously down converting GNSS signals in first and second signal frequency bands;

first and second signal paths receiving GNSS signals corresponding to the first and second signal frequency bands respectively;

a common LO/Synth in said IC and connected to and driving each of said signal paths;

the LO/Synth including a common programmable divider providing a sample clock signal to each of said signal paths and adapted for simultaneously down converting said signals to a lower IF;

first and second ADCs in said IC and each connected to said common programmable divider, each said ADC receiving a down-converted signal as an input and providing a digital signal as an output;

said IC adapted for connections with elements external to said IC;

first and second LNAs located in said IC within said first and second signal paths respectively and each electrically connected to a respective multiplexer output;

first and second first stage BPFs connected to said first and second signal paths respectively;

said first stage BPFs being connected to said first and second LNAs respectively;

said first stage BPFs and said second stage BPFs being electrically connected to said first and second mixers respectively;

a serial peripheral programming interface (SPI) adapted for connection to a device located externally to said IC and adapted for controlling said SPI;

said frequency dividers in the IC being externally programmable via the SPI;

matching components external to said IC connected to the RF input of said IC adapted for external connections, said external matching components adapted for matching signals to respective super bands;

each said signal frequency band comprises a super band of frequencies associated with multiple GNSSs;

said GNSSs are chosen from among the group comprising;

SBAS, GPS, GLONASS and Galileo;

first and second mixers located within said first and second signal paths respectively and electrically connected to said first and second BPFs and said LO/Synth respectively;

said first and second BPFs comprising first stage BPFs;

a first second stage BPF and a second second stage BPF in said first and second signal paths respectively and electrically connected to said first and second mixers respectively;

first and second VGAs in said first and second signal paths respectively and electrically connected to said second stage BPFs;

first and second ADCs in said first and second signal paths respectively and electrically connected to said first and second VGAs respectively;

each of said first and second ADCs receiving an analog signal input from a respective VGA and providing a digital signal output;

each said LO/Synth, said SPI, said mixers, said VGAs and said ADCs being collectively contained in said IC;

said BPFs being located externally to said IC;

said sample clock signal supporting IF subsampling of the analog IF signals in said first and second signal paths;

said sample clock signal being generated by dividing the LO/Synth output by an integer;

an active antenna providing output to said IC;

said IC providing input to a correlator application-specific integrated circuit (ASIC); and

a GNSS solution processor connected to and receiving output from said correlator ASIC.