MRAM HAVING VARIABLE WORD LINE DRIVE POTENTIAL

• US 20100177558A1
• Filed: 07/13/2007
• Published: 07/15/2010
• Est. Priority Date: 08/07/2006
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Sakimura, Noboru, Sugibayashi, Tadahiko, Honda, Takeshi
• Granted Patent: US 8,693,238 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

An MRAM of a spin transfer type according to the invention is provided with a memory cell 10 and a word driver 30. The memory cell 10 has a magnetic resistance element 1 and a selection transistor TR having one of source/drain electrodes which is connected with one end of the magnetic resistance element 1. The word driver 30 drives a word line WL connected with a gate electrode of the selection transistor TR. The word driver 30 changes a drive voltage of the word line WL according to the write data DW to be written in the magnetic resistance element 1.

Claims

1-9. -9. (canceled)

10. A magnetic random access memory of a spin transfer type, comprising:

a memory cell which comprises a magnetic resistance element and said selection transistor having one of source/drain electrodes connected with one end of said magnetic resistance element; and

a word driver configured to drive a word line which is connected with a gate electrode of said selection transistor,

wherein said word driver changes a drive voltage of said word line based on a write data to be written in said magnetic resistance element.

11. The magnetic random access memory according to claim 10, wherein said word driver drives said word line with a first drive voltage, when the write data is a first data, and

said word driver drives said word line with a second drive voltage which is higher than the first drive voltage, when the write data is a second data complementary to said first data.

13. The magnetic random access memory according to claim 11, wherein a source voltage of said selection transistor is a first source voltage, when the write data is the first data, and

the source voltage of said selection transistor is a second source voltage when the write data is the second data.

14. The magnetic random access memory according to claim 11, further comprising:

a common interconnection connected with the other of said source/drain electrodes;

a bit line connected with the other end of said magnetic resistance element; and

a write circuit connected with said bit line,

wherein a voltage of said common interconnection is fixed to a predetermined voltage,

said write circuit applies a voltage lower than the predetermined voltage to said bit line, when the write data is the first data, and

said write circuit applies a voltage higher than the predetermined voltage to said bit line, when the write data is the second data.

15. The magnetic random access memory according to claim 11, further comprising:

a bit line connected with the other of said source/drain electrodes;

a common interconnection connected with the other of said magnetic resistance element; and

a write circuit connected with said bit line,

wherein a voltage of said common interconnection is fixed to a predetermined voltage,

said write circuit applies a voltage lower than the predetermined voltage to said bit line, when the write data is the first data, and

said write circuit applies a voltage higher than the predetermined voltage to said bit line, when the write data is the second data.

16. The magnetic random access memory according to claim 11, further comprising:

a first bit line connected with the other of said source/drain electrodes;

a second bit line connected with the other end of said magnetic resistance element; and

a write circuit connected with said first bit line and said second bit line,

wherein said write circuit applies a voltage lower than that applied to said second bit line, to said first bit line, when the write data is the first data, and

said write circuit applies a voltage higher than that applied to said second bit line, to said first bit line, when the write data is the second data.

17. The magnetic random access memory according to claim 11, wherein said word driver comprises:

a level shifter configured to convert the first drive voltage into said second drive voltage; and

a selector configured to receive the first drive voltage, the second drive voltage outputted from said level shifter and the write data,

said selector outputs the first drive voltage to said word line when the write data is the first data, and

said selector outputs the second drive voltage to said word line when the write data is the second data.

18. A writing method into a magnetic random access memory based on a spin transfer method, wherein said magnetic random access memory has a memory cell which comprises a magnetic resistance element, and a selection transistor having one of source/drain electrodes which is connected with one end of said magnetic resistance element, said writing method comprising:

driving a word line connected with a gate electrode of said selection transistor with a first drive voltage, when a write data to be written into said magnetic resistance element is a first data; and

driving said word line with a second drive voltage higher than the first drive voltage, when the write data is a second data complementary to the first data.