SEMICONDUCTOR DEVICE HAVING A PLURALITY OF SEMICONDUCTOR CONSTRUCTS

• US 20100178731A1
• Filed: 03/08/2010
• Published: 07/15/2010
• Est. Priority Date: 01/10/2006
• Status: Active Grant

• Current Assignee: Casio Computer Company Limited
• Original Assignee: Casio Computer Company Limited
• Inventors: MIHARA, Ichiro
• Granted Patent: US 8,293,574 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A semiconductor device includes a plurality of semiconductor constructs, each of the semiconductor constructs including a semiconductor substrate and external connection electrodes provided on an upper surface of the semiconductor substrate. The semiconductor substrates of the semiconductor constructs are different in a planar-size. The plurality of semiconductor constructs are stacked from bottom to top in descending order of planar-sizes of the semiconductor substrates included in the plurality of semiconductor constructs. An insulating film at least is provided around one semiconductor construct disposed on the top of the plurality of semiconductor constructs and on another semiconductor construct disposed under the one semiconductor construct. Each of the upper surfaces of the plurality of external connection electrodes is exposed from the one semiconductor construct and from the insulating film.

Claims

1. A method for manufacturing a plurality of semiconductor devices, comprising:

preparing a first semiconductor construct including a first semiconductor substrate and a plurality of first external connection electrodes provided in each of a plurality of areas of an upper surface of the first semiconductor substrate, wherein the plurality of semiconductor devices are formed in the plurality of areas, respectively;

preparing a plurality of second semiconductor constructs, each of which includes a second semiconductor substrate, a plurality of second external connection electrodes provided on an upper surface of the second semiconductor substrate, and a sealing film covering the second semiconductor substrate and the second external connection electrodes;

fixing each of the second semiconductor constructs on a central part of one of the areas of the first semiconductor construct by an adhesive bonding layer provided therebetween; and

forming an insulating film on a side of an upper surface of the first semiconductor substrate and upper surfaces of the second semiconductor constructs.

2. The manufacturing method according to claim 1, wherein forming the insulating film comprises forming the insulating film to cover upper surfaces of the first external connection electrodes.

3. The manufacturing method according to claim 2, wherein forming the insulating film is carried out by one of a screen printing method, a spin coat method, and a die coat method.

4. The manufacturing method according to claim 2, further comprising polishing to expose upper surfaces of the second external connection electrodes and an upper surface of the sealing film of the second semiconductor constructs, after forming the insulating film.

5. The manufacturing method according to claim 4, wherein the polishing comprises polishing to expose the upper surfaces of the first external connection electrodes.

6. The manufacturing method according to claim 5, wherein preparing the first semiconductor construct includes forming columnar electrodes electrically connected to connection pads of the first semiconductor construct, as the first external connection electrodes.

7. The manufacturing method according to claim 6, further comprising forming solder balls on the exposed upper surfaces of the first and second external connection electrodes, respectively.

8. The manufacturing method according to claim 4, wherein the first semiconductor construct further includes another sealing film for covering the first external connection electrodes.

9. The manufacturing method according to claim 8, further comprising forming openings in parts of the insulating film which correspond to central parts of the upper surfaces of the first external connection electrodes by laser processing or a photolithographic method, after the polishing.

10. The manufacturing method according to claim 9, further comprising forming first and second upper wiring lines after forming the openings, one end portion of each of the first upper wiring lines being electrically connected to the upper surface of one of the first external connection electrodes through one of the openings, and one end of each of the second upper wiring lines being electrically connected to the upper surface of one of the second external connection electrodes.

11. The manufacturing method according to claim 10, further comprising forming third external connection electrodes on connection pads of the first and second upper wiring lines, respectively, after forming the first and second upper wiring lines.

12. The manufacturing method according to claim 11, further comprising forming solder balls on upper surfaces of the third external connection electrodes, after forming the third external connection electrodes.

13. The manufacturing method according to claim 11, wherein forming the third external connection electrodes comprises forming columnar electrodes as the third external connection electrodes.

14. The manufacturing method according to claim 10, further comprising forming solder balls on upper surfaces of the first and second upper wiring lines, respectively, after forming the first and second upper wiring lines.

15. The manufacturing method according to claim 2, wherein the first semiconductor construct further includes another sealing film for covering the first external connection electrodes.

16. The manufacturing method according to claim 15, further comprising forming openings in parts of the insulating film which correspond to central parts of the upper surfaces of the first and second external connection electrodes by laser processing or a photolithographic method, after forming the insulating film.

17. The manufacturing method according to claim 16, further comprising forming first and second upper wiring lines after forming the openings, one end portion of each of the first upper wiring lines being electrically connected to the upper surface of one of the first external connection electrodes through one of the openings, and one end of each of the second upper wiring lines being electrically connected to the upper surface of one of the second external connection electrodes through one of the openings.

18. The manufacturing method according to claim 17, further comprising forming third external connection electrodes on connection pads of the first and second upper wiring lines, respectively, after forming the first and second upper wiring lines.

19. The manufacturing method according to claim 18, further comprising forming solder balls on upper surfaces of the third external connection electrodes, respectively, after forming the third external connection electrodes.

20. The manufacturing method according to claim 18, wherein forming the third external connection electrodes comprises forming columnar electrodes as the third external connection electrodes.

21. The manufacturing method according to claim 8, wherein the first semiconductor construct includes columnar electrodes electrically connected to connection pads of the first semiconductor construct, as the first external connection electrodes.

22. The manufacturing method according to claim 15, wherein the first semiconductor construct includes columnar electrodes electrically connected to connection pads of the first semiconductor construct, as the first external connection electrodes.

23. The manufacturing method according to claim 1, further comprising polishing an under surface of the first semiconductor construct.

24. The manufacturing method according to claim 1, further comprising dicing the first semiconductor construct to obtain the plurality of semiconductor devices, each of which contains a part of the first semiconductor construct and the second semiconductor construct bonded to the part of the first semiconductor construct.

25. The manufacturing method according to claim 1, wherein the second semiconductor construct includes a plurality of columnar electrodes electrically connected to connection pads of the second semiconductor construct, as the second external connection electrodes.

26. A method for manufacturing a plurality of semiconductor devices, comprising:

preparing a first semiconductor construct including a first semiconductor substrate, a plurality of first external connection electrodes provided in each of a plurality of areas of an upper surface of the first semiconductor substrate, and a first sealing film covering the first semiconductor substrate and the first external connection electrodes;

preparing a plurality of second semiconductor constructs, each of which includes a second semiconductor substrate, a plurality of second external connection electrodes provided on an upper surface of the second semiconductor substrate, and a second sealing film covering the second semiconductor substrate and the second external connection electrodes;

fixing each of the second semiconductor constructs on a central part of one of the areas of the first semiconductor construct by an adhesive bonding layer provided therebetween; and

forming an insulating film on a side of an upper surface of the first semiconductor substrate and upper surfaces of the second semiconductor constructs.